# US 10,373,880 B2 · Semiconductor device and related manufacturing method

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- Number: US 10,373,880 B2
- Document ID: US10373880B2
- Status: Granted
- Kind: B2
- Application number: 15/704,623
- Filed: 2017-09-14
- Published: 2018-01-04
- Granted: 2019-08-06
- Earliest claimed: 2015-05-08
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Deyuan Xiao
- Web page: https://patentgrep.com/patent/US10373880B2

## CPC

- H10D 84/05: using Group III-V technology
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, the method comprising:
preparing a substrate;
providing an n-channel field-effect transistor positioned on the substrate, wherein the n-channel field-effect transistor comprises an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region, and wherein the first n-type channel region is positioned between the n-type silicide source portion and the n-type silicide drain portion and directly contacts each of the n-type silicide source portion and the n-type silicide drain portion, wherein the entire first n-type channel region has a same conductivity type and a same width, and a doping concentration value at a gate-channel interface of the first n-type channel region is higher than a doping concentration value at an inner center portion of the first n-type channel region, and wherein the n-type silicide source portion, the n-type silicide drain portion, and the first n-type channel region have a same height; and
providing a p-channel field-effect transistor positioned on the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first n-type channel region is a first portion of a fin structure, wherein the p-channel field-effect transistor comprises a second n-type channel region, wherein the second n-type channel region is a second portion of the fin structure, and wherein the fin structure is formed of or comprises at least one of germanium, silicon-germanium, and a III-V compound semiconductor material.

### Claim 3 (depends on 2)

The method of claim 2, wherein a doping concentration value of the second n-type channel region is less than a doping concentration value of the first n-type channel region.

### Claim 4 (depends on 1)

The method of claim 1, wherein a doping concentration of the first n-type channel region decreases from the gate-channel interface of the first n-type channel region to the inner center portion of the first n-type channel region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the p-channel field-effect transistor comprises a p-type silicide source portion, a p-type silicide drain portion, and a second n-type channel region, and wherein the second n-type channel region is positioned between the p-type silicide source portion and the p-type silicide drain portion.

### Claim 6 (depends on 1)

The method of claim 1, wherein the p-channel field-effect transistor comprises a first p-type source portion, a second p-type source portion, a first p-type drain portion, a second p-type drain portion, and a second n-type channel region, wherein the second n-type channel region is positioned between the first p-type source portion and the first p-type drain portion, wherein the first p-type source portion and the first p-type drain portion are positioned between the second p-type source portion and the second p-type drain portion, and wherein a doping concentration value of the first p-type source portion is less than a doping concentration value of the second p-type source portion.

### Claim 7 (depends on 6)

The method of claim 6, wherein the p-channel field-effect transistor comprises a p-type silicide source portion and a p-type silicide drain portion, and wherein the second p-type source portion and the second p-type drain portion are positioned between the p-type silicide source portion and the p-type silicide drain portion.