# US 10,373,879 B2 · Semiconductor device with contracted isolation feature and formation method thereof

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- Number: US 10,373,879 B2
- Document ID: US10373879B2
- Status: Granted
- Kind: B2
- Application number: 15/600,919
- Filed: 2017-05-22
- Published: 2018-11-01
- Granted: 2019-08-06
- Earliest claimed: 2017-04-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Dian-Sheg Yu; Ren-Fen Tsui; Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US10373879B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 89/10: Integrated device layouts
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming a first dummy gate structure over a substrate;
forming gate spacers over the substrate;
cutting the first dummy gate structure to form separated dummy gate portions;
forming a dielectric feature between the dummy gate portions;
performing a thermal process to the dielectric feature to contract the dielectric feature, the contraction of the dielectric feature deforming at least one of the gate spacers such that a distance between the gate spacers is increased; and
forming a second dummy gate structure prior to performing the thermal process, wherein the contraction of the dielectric feature enlarges the second dummy gate structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the dielectric feature comprises depositing a flowable dielectric material between the dummy gate portions.

### Claim 3 (depends on 2)

The method of claim 2, wherein the thermal process densifies the flowable dielectric material.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a dielectric liner between the dummy gate portions prior to the forming the dielectric feature, wherein the forming the dielectric feature comprises forming the dielectric feature into a recess of the dielectric liner.

### Claim 5 (depends on 4)

The method of claim 4, wherein the dielectric feature has higher flowability than that of the dielectric liner before the performing the thermal process.

### Claim 6 (depends on 4)

The method of claim 4, wherein the dielectric liner is a silicon nitride layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming the dielectric feature comprises forming a flowable oxide into the recess of the silicon nitride layer.

### Claim 8 (depends on 4)

The method of claim 4, wherein the contraction of the dielectric feature deforms the dielectric liner.

### Claim 9 (depends on 4)

The method of claim 4, wherein the contraction of the dielectric feature is greater than contraction of the dielectric liner during the thermal process.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
removing the enlarged second dummy gate structure to form a gate trench between the gate spacers; and
forming a gate metal into the gate trench.

### Claim 11 (depends on 1)

The method of claim 1, further comprising forming a third dummy gate structure between the first and second dummy gate structures.

### Claim 12 (depends on 11)

The method of claim 11, further comprising replacing the third dummy gate structure with a gate metal.

### Claim 13

A method of forming a semiconductor device, comprising:
forming a first dummy gate structure over a substrate;
forming gate spacers over the substrate;
forming an opening in the first dummy gate structure;
forming an isolation feature into the opening in the first dummy gate structure;
contracting the isolation feature, thereby deforming at least one of the gate spacers to increase a distance between the gate spacers;
forming a second dummy gate structure prior to contracting the isolation feature, wherein contracting the isolation feature expands the second dummy gate structure; and
replacing the expanded second dummy gate structure with a gate metal.

### Claim 14 (depends on 13)

The method of claim 13, wherein the isolation feature is formed using a flowable chemical vapor deposition process, and wherein the contracting the isolation feature comprises performing an annealing process after the flowable chemical vapor deposition process.

### Claim 15 (depends on 13)

The method of claim 13, wherein the isolation feature is a flowable oxide before the contracting.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
forming a dielectric liner lining a sidewall of the opening in the first dummy gate structure, wherein the isolation feature is filled into a recess of the dielectric liner.

### Claim 17

A method of forming a semiconductor device, wherein the method comprises:
forming a plurality of fins respectively protruding from a substrate;
forming a first dummy gate structure and a second dummy gate structure crossing the fins;
forming a gate spacer adjoining a side of the second dummy gate structure;
growing source/drain devices on both sides of each of the first dummy gate structure and the second dummy gate structure on the fins;
performing a cut operation on the first dummy gate structure, thereby forming an opening;
depositing a dielectric feature in the opening;
performing a thermal operation to contract the dielectric feature, thereby deforming the gate spacer adjoining the second dummy gate structure;
removing the second dummy gate structure, thereby forming a gate trench; and
depositing a metal gate structure in the gate trench.

### Claim 18 (depends on 17)

The method of claim 17, depositing the dielectric feature in the opening further comprises:
forming a dielectric liner in the opening; and
forming a dielectric filling over the dielectric liner.

### Claim 19 (depends on 18)

The method of claim 18, wherein the dielectric filling has higher flowability than that of the dielectric liner before performing the thermal operation.

### Claim 20

The method of 17, further comprising performing the thermal operation to expand the second dummy gate structure.