# US 10,373,877 B1 · Methods of forming source/drain contact structures on integrated circuit products

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- Number: US 10,373,877 B1
- Document ID: US10373877B1
- Status: Granted
- Kind: B1
- Application number: 15/986,390
- Filed: 2018-05-22
- Granted: 2019-08-06
- Earliest claimed: 2018-05-22
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Haiting Wang; Hong Yu; Hui Zang; Wei Zhao; Yue Zhong; Guowei Xu; Laertis Economikos; Jerome Ciavatti; Scott Beasor
- Web page: https://patentgrep.com/patent/US10373877B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 50/73: {using masks for insulating materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

## Claims

### Claim 1

A method, comprising:
forming a plurality of transistor devices on a semiconductor substrate, each of said transistor devices comprising a sacrificial gate structure, a gate cap, source/drain regions, source/drain epitaxial semiconductor material in said source/drain regions, a contact etch stop layer positioned above said source/drain epitaxial semiconductor material and an insulating material positioned above said contact etch stop layer;
forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein said etching process sequence is adapted to sequentially remove said insulating material, said contact etch stop layer and said source/drain epitaxial semiconductor material;
forming a contact isolation structure in each of said contact isolation cavities;
after forming said contact isolation structures, removing said sacrificial gate structures so as to form a plurality of replacement gate cavities; and
forming a final gate structure in each of said plurality of replacement gate cavities.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
removing portions of said insulating material and said contact etch stop layer to expose said source/drain epitaxial semiconductor material in said source/drain regions and thereby form source/drain contact openings that are bounded in at least one direction by a plurality of said contact isolation structures; and
forming a conductive source/drain metallization structure in said source/drain contact openings.

### Claim 3 (depends on 1)

The method of claim 1, wherein said contact isolation structures are comprised of a material that is different than said insulating material such that said insulating material is selectively removable relative to said contact isolation structures by etching.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing said etching process sequence comprises:
performing a first etching process that is adapted to remove said insulating material selectively relative to said contact etch stop layer;
performing a second etching process that is adapted to remove said contact etch stop layer selectively relative to said source/drain epitaxial semiconductor material and said insulating material; and
performing a third etching process that is adapted to remove said source/drain epitaxial semiconductor material selectively relative to said insulating material and said contact etch stop layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein said transistor devices are FinFET devices.

### Claim 6 (depends on 1)

The method of claim 1, further comprising;
forming a gate-cut patterned etch mask above said transistor devices;
forming a plurality of etching processes through said gate-cut patterned etch mask to remove exposed portions of said gate caps and a portion of an axial length of each of said sacrificial gate structures so as to form a plurality of gate-cut cavities that are laterally bounded by a sidewall spacer formed adjacent each of said gate structures; and
forming a gate-cut isolation structure in each of said gate-cut cavities at the same time as said contact isolation structures are formed in said contact isolation cavities.

### Claim 7 (depends on 6)

The method of claim 6, wherein said gate-cut cavities are formed prior to the formation of said contact isolation cavities.

### Claim 8 (depends on 2)

The method of claim 2, wherein said conductive source/drain metallization structures are bounded in at least one direction by said plurality of said contact isolation structures.

### Claim 9 (depends on 4)

The method of claim 4, wherein said first etching process is an anisotropic etching process, said second etching process is an anisotropic etching process and said third etching process is an isotropic etching process.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming said plurality of contact isolation cavities comprises performing said etching process sequence multiple times.

### Claim 11 (depends on 1)

The method of claim 1, wherein said sacrificial gate structure comprises a sacrificial gate insulation layer and a sacrificial gate electrode, said sacrificial gate electrode comprising one of polysilicon or amorphous silicon.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming said plurality of contact isolation cavities comprises:
sequentially forming a plurality of patterned etch masks above said transistor devices; and
after forming each of said patterned etch masks, performing said etching process sequence through said patterned etch masks.

### Claim 13

A method, comprising:
forming a plurality of transistor devices on a semiconductor substrate, each of said transistor devices comprising a sacrificial gate structure, a gate cap, source/drain regions, source/drain epitaxial semiconductor material in said source/drain regions, a contact etch stop layer positioned above said source/drain epitaxial semiconductor material and an insulating material positioned above said contact etch stop layer;
sequentially forming a plurality of patterned etch masks above said transistor devices;
after forming each of said patterned etch masks, performing an etching process sequence through said patterned etch masks, wherein said etching process sequence is adapted to sequentially remove said insulating material, said contact etch stop layer and said source/drain epitaxial semiconductor material so as to form a plurality of contact isolation cavities;
forming a contact isolation structure in each of said plurality of contact isolation cavities;
after forming said contact isolation structures, removing said sacrificial gate structures so as to form a plurality of replacement gate cavities; and
forming a final gate structure in each of said plurality of replacement gate cavities.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
removing portions of said insulating material and said contact etch stop layer to expose said source/drain epitaxial semiconductor material in said source/drain regions and thereby form source/drain contact openings that are bounded in at least one direction by a plurality of said contact isolation structures; and
forming a conductive source/drain metallization structure in said source/drain contact openings.

### Claim 15 (depends on 13)

The method of claim 13, wherein said contact isolation structures are comprised of a material that is different than said insulating material such that said insulating material is adapted to be selectively removed relative to said contact isolation structures by etching.

### Claim 16 (depends on 14)

The method of claim 14, wherein sequentially forming said plurality of patterned etch masks above said transistor devices comprises sequentially forming at least three patterned etch masks above said transistor devices and wherein the method comprises performing said etching process sequence at least three times.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
forming a gate-cut patterned etch mask above said transistor devices;
forming a plurality of etching processes through said gate-cut patterned etch mask to remove exposed portions of said gate caps and a portion of an axial length of each of said sacrificial gate structures so as to form a plurality of gate-cut cavities that are laterally bounded by a sidewall spacer formed adjacent each of said sacrificial gate structures; and
forming a gate-cut isolation structure in each of said gate-cut cavities at the same time as said contact isolation structures are formed in said contact isolation cavities.

### Claim 18 (depends on 17)

The method of claim 17, wherein said gate-cut cavities are formed prior to the formation of said contact isolation cavities.

### Claim 19

A method, comprising:
forming a plurality of transistor devices on a semiconductor substrate, each of said transistor devices comprising a sacrificial gate structure, a gate cap, source/drain regions, source/drain epitaxial semiconductor material in said source/drain regions, a contact etch stop layer positioned above said source/drain epitaxial semiconductor material and an insulating material positioned above said contact etch stop layer;
forming a patterned etch mask above said transistor devices;
after forming said patterned etch mask, performing an etching process sequence through said patterned etch mask, wherein said etching process sequence is adapted to sequentially remove said insulating material, said contact etch stop layer and said source/drain epitaxial semiconductor material so as to form a plurality of contact isolation cavities;
forming a contact isolation structure in each of said plurality of contact isolation cavities;
after forming said contact isolation structures, removing said sacrificial gate structures so as to form a plurality of replacement gate cavities; and
forming a final gate structure in each of said plurality of replacement gate cavities.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a gate-cut patterned etch mask above said transistor devices;
forming a plurality of etching processes through said gate-cut patterned etch mask to remove exposed portions of said gate caps and a portion of an axial length of each of said sacrificial gate structures so as to form a plurality of gate-cut cavities that are laterally bounded by a sidewall spacer formed adjacent each of said sacrificial gate structures; and
forming a gate-cut isolation structure in each of said gate-cut cavities at the same time as said contact isolation structures are formed in said contact isolation cavities.