# US 10,373,876 B2 · Method for preventing dishing during the manufacture of semiconductor devices

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- Number: US 10,373,876 B2
- Document ID: US10373876B2
- Status: Granted
- Kind: B2
- Application number: 15/953,537
- Filed: 2018-04-16
- Published: 2018-08-16
- Granted: 2019-08-06
- Earliest claimed: 2015-12-28
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Shih-Yin Hsiao; Kuan-Liang Liu
- Web page: https://patentgrep.com/patent/US10373876B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/01: Manufacture or treatment
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/282: {of inorganic materials}
- H10P 95/062: {involving a dielectric removal step}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having at least a first area with a plurality of metal gates and a second area adjacent to the first area;
a patterned contact etch stop layer (CESL) formed in the first area and the second area;
a patterned dielectric layer formed on the patterned CESL, wherein adjacent metal gates are separated by the patterned CESL and the patterned dielectric layer; and
a pattern comprising patterned underlying nitrides being embedded in the patterned dielectric layer within the second area, wherein the pattern comprising the patterned underlying nitrides is a pattern comprising plural discrete nitride sections encapsulated by the patterned dielectric layer,
wherein the pattern comprising the patterned underlying nitrides is separated from the patterned CESL by the patterned dielectric layer, and the patterned dielectric layer covers top surfaces, side surfaces and bottom surfaces of the patterned underlying nitrides.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the pattern comprising the patterned underlying nitrides is parallel to the substrate.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the pattern comprising the patterned underlying nitrides has a uniform thickness.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the plural discrete nitride sections are plural discrete nitride stripes, plural discrete circular nitride blocks, plural discrete rectangular nitride blocks or plural discrete square nitride blocks, or the plural discrete nitride sections form a net-like nitride pattern.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the patterned CESL comprises nitride and the patterned dielectric layer comprises oxide.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the second area is an area with a density of the plurality of metal gates lower than a density of the plurality of metal gates in the first area.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the second area is an area without any metal gate.