# US 10,373,875 B1 · Contacts formed with self-aligned cuts

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- Number: US 10,373,875 B1
- Document ID: US10373875B1
- Status: Granted
- Kind: B1
- Application number: 15/928,783
- Filed: 2018-03-22
- Granted: 2019-08-06
- Earliest claimed: 2018-03-22
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Ruilong Xie; Daniel Jaeger; Chanro Park; Laertis Economikos; Haiting Wang; Hui Zang
- Web page: https://patentgrep.com/patent/US10373875B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 50/73: {using masks for insulating materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. In one process, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. In another process, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

## Claims

### Claim 1

A method comprising:
forming a first source/drain region and a second source/drain region adjacent to a temporary gate structure;
forming a sacrificial layer over the first source/drain region and the second source/drain region;
etching a trench in the sacrificial layer that is disposed between the first source/drain region and the second source/drain region;
depositing a first dielectric material in the trench to form a dielectric pillar between the first source/drain region and the second source/drain region;
after depositing the first dielectric material in the trench, forming a fill layer over the first source/drain region and the second source/drain region;
after forming the fill layer, replacing the temporary gate structure with a functional gate structure;
after replacing the temporary gate structure with the functional gate structure, removing the fill layer; and
forming a conductive layer having a first portion contacting the first source/drain region and a second portion contacting the second source/drain region,
wherein the dielectric pillar separates the first portion of the conductive layer from the second portion of the conductive layer.

### Claim 2 (depends on 1)

The method of claim 1 wherein the sacrificial layer is composed of an organic planarization layer material.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
before depositing the first dielectric material in the trench, depositing a dielectric liner on sidewalls of the trench.

### Claim 4 (depends on 1)

The method of claim 1 wherein etching the trench in the sacrificial layer comprises:
forming a lithography stack over the sacrificial layer;
forming an opening in the lithography stack to expose a portion of the sacrificial layer; and
etching the exposed portion of the sacrificial layer.

### Claim 5 (depends on 1)

The method of claim 1 wherein etching the trench in the sacrificial layer comprises:
etching an upper portion of the trench in the sacrificial layer, the upper portion exposing a portion of the first source/drain region and a portion of the second source/drain region;
forming a dielectric spacer on sidewalls of the upper portion of the trench; and
etching a lower portion of the trench in the sacrificial layer, the dielectric liner material protecting remaining portions of the sacrificial layer arranged over the first source/drain region and the second source/drain region.

### Claim 6 (depends on 5)

The method of claim 5 wherein etching the lower portion of the trench comprises:
anisotropically etching the sacrificial layer disposed between the first source/drain region and the second source/drain region; and
isotropically etching the sacrificial layer disposed below the portion of the first source/drain region and below the portion of the second source/drain region.

### Claim 7 (depends on 5)

The method of claim 5 further comprising:
depositing a dielectric liner on sidewalls of the lower portion of the trench, on the exposed portion of the first source/drain region, and on the exposed portion of the second source/drain region.

### Claim 8 (depends on 7)

The method of claim 7 wherein the dielectric liner and the dielectric spacer are each composed of a second dielectric material.

### Claim 9 (depends on 5)

The method of claim 5 further comprising:
before forming the dielectric spacer, etching an outer portion of the first source/drain region and an outer portion of the second source/drain region.