# US 10,373,874 B2 · Middle of the line subtractive self-aligned contacts

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- Number: US 10,373,874 B2
- Document ID: US10373874B2
- Status: Granted
- Kind: B2
- Application number: 15/333,878
- Filed: 2016-10-25
- Published: 2017-06-08
- Granted: 2019-08-06
- Earliest claimed: 2015-12-07
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Joshua M. Rubin; Balasubramanian Pranatharthiharan
- Web page: https://patentgrep.com/patent/US10373874B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/834: {comprising FinFETs}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0158: {the components including FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.

## Claims

### Claim 1

A semiconductor device, comprising:
first and second gate structures;
a source/drain region formed between the first and second gate structures; and
a continuous portion of conductive material formed in a trench located above the source/drain region between the first and second gate structures and to a height above the first and second gate structures, the continuous portion of conductive material monolithically forming a trench line disposed over a plurality of semiconductor fins and a self-aligned contact disposed directly on the trench line over a single semiconductor fin;
the self-aligned contact and the trench line being free of interfaces between the self-aligned contact and the trench line to avoid resistive losses.

### Claim 2 (depends on 1)

The device as recited in claim 1, further comprising a liner formed in the trench on which the continuous portion of conductive material is formed.

### Claim 3 (depends on 2)

The device as recited in claim 2, wherein the liner is disposed between and in direct contact with the source/drain regions and the trench lines.

### Claim 4 (depends on 2)

The device as recited in claim 2, wherein the liner extends along sidewalls of the trench line and the self-aligned contact is linerless.

### Claim 5 (depends on 2)

The device as recited in claim 2, wherein the liner includes TiN.

### Claim 6 (depends on 1)

The device as recited in claim 1, further comprising an interlevel dielectric layer formed to the height to isolate the self-aligned contact.

### Claim 7 (depends on 1)

The device as recited in claim 1, wherein the self-aligned contact has a different size than the trench line.

### Claim 8 (depends on 1)

The device as recited in claim 1, wherein the device is included within an integrated circuit.

### Claim 9 (depends on 1)

The device as recited in claim 1, wherein each of the gate structures includes a gate conductor on a gate dielectric, and wherein the gate conductor includes at least one material selected from the group consisting of: W, Al, TiC, and TiN.

### Claim 10

A semiconductor device, comprising: first and second gate structures; a source/drain region formed between the first and second gate structures; a liner formed in a trench located above the source/drain region between the first and second gate structures; a continuous portion of conductive material formed in on the liner in the trench to a height above the first and second gate structures, the continuous portion of conductive material monolithically forming a trench line and a self-aligned contact disposed directly on the trench line, wherein the liner extends along sidewalls of the trench line and the self-aligned contact is linerless, and wherein the self-aligned contact is disposed over a single semiconductor fin and the trench line is disposed over a plurality of semiconductor fins; the self-aligned contact and the trench line being free of interfaces between the self-aligned contact and the trench line to avoid resistive losses.

### Claim 11 (depends on 10)

The device as recited in claim 10, further comprising an interlevel dielectric layer formed to the height to isolate the self-aligned contact.

### Claim 12 (depends on 10)

The device as recited in claim 10, wherein the self-aligned contact has a different size than the trench line.

### Claim 13 (depends on 10)

The device as recited in claim 10, wherein the liner is disposed between and in direct contact with the source/drain regions and the trench lines.

### Claim 14 (depends on 10)

The device as recited in claim 10, wherein the device is included within an integrated circuit.

### Claim 15 (depends on 10)

The device as recited in claim 10, wherein each of the gate structures includes a gate conductor on a gate dielectric, and wherein the gate conductor includes at least one material selected from the group consisting of: W, Al, TiC, and TiN.

### Claim 16 (depends on 10)

The device as recited in claim 10, wherein the liner includes TiN.