# US 10,373,873 B1 · Gate cut in replacement metal gate process

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- Number: US 10,373,873 B1
- Document ID: US10373873B1
- Status: Granted
- Kind: B1
- Application number: 15/933,708
- Filed: 2018-03-23
- Granted: 2019-08-06
- Earliest claimed: 2018-03-23
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Chanro Park; Ruilong Xie; Kangguo Cheng; Laertis Economikos
- Web page: https://patentgrep.com/patent/US10373873B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Gate isolation methods and structures for a FinFET device leverage the definition and formation of a gate cut opening within a sacrificial gate layer prior to patterning the sacrificial gate layer to form a sacrificial gate. The gate cut opening formed in the sacrificial gate layer is filled with a sacrificial isolation layer. After forming source/drain junctions over source/drain regions of a fin, the sacrificial isolation layer is replaced with an isolation layer, and the sacrificial gate is replaced with a functional gate.

## Claims

### Claim 1

A method of forming a device, comprising:
forming a plurality of fins over a semiconductor substrate;
forming a dielectric layer over the substrate and between the fins;
depositing a sacrificial gate layer over the fins and over the dielectric layer;
forming a first opening in the sacrificial gate layer between a pair of the fins, wherein the dielectric layer is exposed at a bottom of the first opening;
depositing a sacrificial isolation layer within the first opening;
etching the sacrificial gate layer and the sacrificial isolation layer to form a sacrificial gate;
forming a spacer layer over sidewalls of the sacrificial gate;
removing the sacrificial isolation layer from within the first opening after forming the spacer layer;
depositing an isolation layer within the first opening;
etching remaining portions of the sacrificial gate layer selectively with respect to the isolation layer to form a second opening;
forming a gate dielectric layer within the second opening; and
forming a gate conductor layer over the gate dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the sacrificial gate layer comprises amorphous silicon and the sacrificial isolation layer comprises silicon germanium.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a critical dimension modification layer over sidewalls of the first opening prior to depositing the sacrificial isolation layer within the first opening.

### Claim 4 (depends on 3)

The method of claim 3, wherein the critical dimension modification layer comprises amorphous silicon.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming source/drain junctions over source/drain regions of at least one of the fins using the sacrificial gate and the spacer layer as an alignment mask prior to removing the sacrificial isolation layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sacrificial isolation layer is removed from within the first opening prior to removing the remaining portions of the sacrificial gate layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the fin is exposed at a bottom of the second opening prior to forming the gate dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising polishing the sacrificial isolation layer such that a top surface of the sacrificial isolation layer is co-planar with a top surface of the sacrificial gate layer.

### Claim 9

A method of forming a device, comprising:
forming a plurality of fins over a substrate;
depositing a sacrificial gate layer over the fins;
forming a first opening in the sacrificial gate layer between a pair of the fins;
depositing a sacrificial isolation layer within the first opening;
etching the sacrificial gate layer and the sacrificial isolation layer to form a sacrificial gate;
forming a spacer layer over sidewalls of the sacrificial gate;
removing the sacrificial isolation layer from within the first opening after forming the spacer layer;
depositing an isolation layer within the first opening;
removing remaining portions of the sacrificial gate layer to form a second opening, wherein at least one of the plurality of fins is exposed at a bottom of the second opening;
forming a gate dielectric layer within the second opening; and
forming a gate conductor layer over the gate dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the sacrificial gate layer comprises amorphous silicon and the sacrificial isolation layer comprises silicon germanium.

### Claim 11 (depends on 9)

The method of claim 9, further comprising forming a critical dimension modification layer over sidewalls of the first opening prior to depositing the sacrificial isolation layer within the first opening.

### Claim 12 (depends on 11)

The method of claim 11, wherein the critical dimension modification layer comprises amorphous silicon.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming source/drain junctions over source/drain regions of at least one of the fins using the sacrificial gate and the spacer layer as an alignment mask prior to removing the sacrificial isolation layer.

### Claim 14 (depends on 9)

The method of claim 9, wherein the sacrificial isolation layer is removed from within the first opening prior to removing the remaining portions of the sacrificial gate layer.

### Claim 15 (depends on 9)

The method of claim 9, further comprising polishing the sacrificial isolation layer such that a top surface of the sacrificial isolation layer is co-planar with the top surface of the sacrificial gate layer.