# US 10,373,870 B2 · Semiconductor device and method of packaging

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- Number: US 10,373,870 B2
- Document ID: US10373870B2
- Status: Granted
- Kind: B2
- Application number: 15/967,536
- Filed: 2018-04-30
- Published: 2018-09-06
- Granted: 2019-08-06
- Earliest claimed: 2010-02-16
- Assignees: DECA Technologies Inc.
- Applicants: DECA Technologies Inc.
- Inventors: Christopher M. Scanlan; Timothy L. Olson
- Web page: https://patentgrep.com/patent/US10373870B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/656: Fan-in layouts
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/90: Bond pads, in general
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/144: {the encapsulations comprising foils}
- H10W 74/473: {containing a filler}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- Y02P 80/30: Reducing waste in manufacturing processes; Calculations of released waste quantities
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;
conductive interconnects comprising first ends coupled to the contact pads, second ends opposite the first ends, and side surfaces extending between the first ends and the second ends, the second ends of the conductive interconnects offset from the active surface by a height of at least 8 micrometers (μm);
a single encapsulant contacting the four side surfaces of the semiconductor die and side surfaces of the conductive interconnects, the single encapsulant further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;
openings formed through the planar surface of the single encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 μm; and
a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending into the openings to electrically connect with the conductive interconnects.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the conductive interconnects comprise copper studs or redistribution layer (RDL) traces.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the build-up interconnect layer comprises conductive bumps coupled to the redistribution layer (RDL).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the planar surface is free from a conductive residue formed by grinding the single encapsulant and the conductive interconnects.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a backside coating contacting a backside of the semiconductor die.

### Claim 6 (depends on 4)

A method of making the semiconductor device of claim 4, further comprising:
grinding a surface of the single encapsulant to expose the conductive interconnects, to form the planar surface, and to form the conductive residue across the planar surface; and
etching the conductive residue and the exposed conductive interconnects to remove the conductive residue at the planar surface and to reduce a height of the conductive interconnects to form the second ends of the conductive interconnects offset from the planar surface by a distance greater than 1 μm.

### Claim 7

A semiconductor device comprising:
a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;
conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends;
a single encapsulant contacting the four side surfaces of the semiconductor die and side surfaces of the conductive interconnects, the single encapsulant further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;
openings formed through the planar surface of the single encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 micrometers (μm); and
a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending into the openings to electrically connect with the conductive interconnects.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the conductive interconnects comprise copper studs or redistribution layer (RDL) traces.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the build-up interconnect layer comprises conductive bumps coupled to the redistribution layer (RDL).

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the planar surface is free from a conductive residue formed by grinding the single encapsulant and the conductive interconnects.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, further comprising a backside coating contacting a backside of the semiconductor die.

### Claim 12 (depends on 10)

A method of making the semiconductor device of claim 10, further comprising:
grinding a surface of the single encapsulant to expose the conductive interconnects, to form the planar surface, and to form the conductive residue across the planar surface; and
etching the conductive residue and the exposed conductive interconnects to remove the conductive residue at the planar surface and to reduce a height of the conductive interconnects to form the second ends of the conductive interconnects offset from the planar surface by a distance greater than 1 μm.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein a back surface of the semiconductor die is exposed at a periphery of the semiconductor device.

### Claim 14

A semiconductor device comprising:
a semiconductor die comprising an active surface and contact pads disposed over the active surface;
conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends;
an encapsulant comprising a planar surface disposed over the active surface of the semiconductor die, the encapsulant comprising openings with a distance greater than or equal to 1 micrometer (μm) that extend from the planar surface of the encapsulant to the conductive interconnects; and
a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending across the planar surface of the encapsulant and into the openings to electrically connect with the conductive interconnects.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the conductive interconnects comprise copper studs or redistribution layer (RDL) traces.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein a back surface of the semiconductor die is exposed at a periphery of the semiconductor device.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the planar surface is free from a conductive residue formed by grinding the encapsulant and the conductive interconnects.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further comprising a backside coating contacting a backside of the semiconductor die.

### Claim 19 (depends on 17)

A method of making the semiconductor device of claim 17, further comprising:
grinding a surface of the encapsulant to expose the conductive interconnects, to form the planar surface, and to form the conductive residue across the planar surface; and
etching the conductive residue and the exposed conductive interconnects to remove the conductive residue at the planar surface and to reduce a height of the conductive interconnects to form the second ends of the conductive interconnects offset from the planar surface by a distance greater than 1 μm.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein:
the semiconductor die comprises four side surfaces;
the conductive interconnects comprise side surfaces extending from the first ends to the second ends; and
the encapsulant contacts the four side surfaces of the semiconductor die and the side surfaces of the conductive interconnects.