# US 10,373,867 B2 · Cobalt contact and interconnect structures

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- Number: US 10,373,867 B2
- Document ID: US10373867B2
- Status: Granted
- Kind: B2
- Application number: 15/801,933
- Filed: 2017-11-02
- Published: 2018-07-12
- Granted: 2019-08-06
- Earliest claimed: 2017-01-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Hari P. Amanapu; Raghuveer R. Patlolla; Cornelius Brown Peethala; Chih-Chao Yang
- Web page: https://patentgrep.com/patent/US10373867B2

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/064: {by modifying the conductivity of conductive parts, e.g. by alloying}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.

## Claims

### Claim 1

A method for forming an integrated circuit comprising:
providing a patterned substrate comprising a trench structure, a via structure or combinations thereof in a dielectric layer;
depositing a metal liner layer onto the patterned substrate;
depositing cobalt onto the metal liner layer;
depositing a stress control layer onto the cobalt; and
annealing the patterned substrate to increase grain size of the cobalt.

### Claim 2 (depends on 1)

The method of claim 1, wherein depositing the cobalt onto the metal liner forms an overburden of the cobalt onto the patterned substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein the cobalt is deposited by chemical vapor deposition.

### Claim 4 (depends on 1)

The method of claim 1, wherein the stress control layer comprises tantalum, titanium, ruthenium, iridium, tungsten, cobalt, nitrides thereof, or mixtures thereof.

### Claim 5 (depends on 1)

The method of claim 1, wherein the stress control layer is at a thickness less than about 500 Angstroms.

### Claim 6 (depends on 1)

The method of claim 1, wherein the trench structure, the via structure, or combinations thereof have an aspect ratio greater than 2:1.

### Claim 7 (depends on 1)

The method of claim 1, wherein annealing is subsequent to a chemical mechanical planarization process.

### Claim 8 (depends on 1)

The method of claim 1, wherein annealing the patterned substrate forms a silicide region at a bottom of the trench structure, the via structure, or combinations thereof.

### Claim 9 (depends on 1)

The method of claim 1, wherein the stress control layer is at a thickness of about 50 Angstroms to about 150 Angstroms.

### Claim 10 (depends on 1)

The method of claim 1, wherein annealing comprises heating the patterned substrate to a temperature of about 200° C. to about 400° C. for a period of time of about 30 minutes to about 4 hours.

### Claim 11

A method for forming a contact structure or an interconnect structure in a semiconductor structure, comprising:
forming at least one opening extending through an interlayer dielectric;
filling the at least one opening with cobalt and forming an overburden of cobalt;
depositing a stress control layer on the overburden, wherein the stress control layer is configured to prevent diffusion of the cobalt into the stress control layer;
annealing the semiconductor structure; and
removing the stress control layer and the overburden subsequent to the annealing.

### Claim 12 (depends on 11)

The method of claim 11, wherein annealing comprises heating the semiconductor structure to a temperature of about 200° C. to about 400° C. for a period of time of about 30 minutes to about 4 hours.

### Claim 13 (depends on 11)

The method of claim 11, further comprising cleaning a bottom surface of the at least one opening prior to annealing to form a silicide region subsequent to annealing.

### Claim 14 (depends on 12)

The method of claim 12, wherein removing the stress control layer comprises a wet stripping process, and removing the overburden comprises a chemical mechanical planarization process.

### Claim 15 (depends on 11)

The method of claim 11, wherein the stress control layer comprises tantalum, titanium, ruthenium, iridium, tungsten, cobalt, nitrides thereof, or mixtures thereof.

### Claim 16 (depends on 11)

The method of claim 11, wherein the filling the at least one opening with the cobalt comprises chemical vapor deposition and forming the overburden comprises plasma vapor deposition.

### Claim 17 (depends on 11)

The method of claim 11, wherein the stress control layer is at a thickness less than about 500 Angstroms.

### Claim 18 (depends on 11)

The method of claim 11, wherein a height and a width of the at least one opening is at an aspect ratio of at least about 10:1.

### Claim 19 (depends on 11)

The method of claim 11, further comprising depositing a liner layer on the semiconductor structure prior to filling the at least one opening with cobalt and forming the overburden of cobalt.