# US 10,373,866 B1 · Method of forming metal insulator metal capacitor with extended capacitor plates

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- Number: US 10,373,866 B1
- Document ID: US10373866B1
- Status: Granted
- Kind: B1
- Application number: 15/971,840
- Filed: 2018-05-04
- Granted: 2019-08-06
- Earliest claimed: 2018-05-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chih-Chao Yang; Theodorus E Standaert
- Web page: https://patentgrep.com/patent/US10373866B1

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/694: {comprising noble metals or noble metal oxides}
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10D 1/711: {having non-planar surfaces, e.g. formed by texturisation}
- H10D 1/716: {having vertical extensions}
- H10P 14/40: of conductive or resistive materials
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 50/667: {by liquid etching only}
- H10P 95/04: {Planarisation of conductive or resistive materials}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10P 50/262: {by physical means only}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A capacitor structure and a method for constructing the structure are described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.

## Claims

### Claim 1

A method for fabricating a metal insulator metal in a dielectric trench for an integrated circuit device comprising:
providing a first dielectric layer on a substrate;
etching a trench in the first dielectric layer;
depositing a bottom capacitor plate metal in the trench;
creating an extended top face in the bottom capacitor plate metal, wherein the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions;
forming a high-k dielectric layer over the extended top face of the bottom capacitor plate; and
depositing a top capacitor plate in a remainder portion of the trench on top of the high-k dielectric layer.

### Claim 2 (depends on 1)

The method as recited in claim 1, further comprising:
depositing a barrier layer prior to depositing the bottom capacitor plate metal; and
after the creation of the extended top face, etching the barrier layer disposed on a sidewall of the dielectric and higher than a location that the extended top face and the barrier layer meet.

### Claim 3 (depends on 2)

The method as recited in claim 2, wherein the high-k dielectric layer is also formed on the sidewall of the dielectric and higher than a location that the extended top face and the barrier layer meet.

### Claim 4 (depends on 3)

The method as recited in claim 3, further comprising:
performing a planarization step after depositing the bottom capacitor plate metal in the trench; and
performing a planarization step after depositing the top capacitor plate metal in the trench.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein the extended top face of the bottom capacitor plate has a rounded profile.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein the extended top face of the bottom capacitor plate has a ridge line profile.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein an angular sputtering process is performed to create the extended top face of the bottom capacitor plate.

### Claim 8 (depends on 7)

The method as recited in claim 7, wherein the sputtering direction is between 10 degrees to 80 degrees from the horizontal surface.

### Claim 9 (depends on 1)

The method as recited in claim 1, wherein a wet etching sputtering process is performed to create the extended top face.