# US 10,373,861 B1 · FinFET with curved STI > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,861 B1 - Document ID: US10373861B1 - Status: Granted - Kind: B1 - Application number: 16/026,077 - Filed: 2018-07-03 - Granted: 2019-08-06 - Earliest claimed: 2018-06-07 - Assignees: United Microelectronics Corp. - Applicants: United Microelectronics Corp. - Inventors: Chi-Ying Hsieh; Chih-Jung Chen; Chien-Hung Chen; Chih-Yueh Li; Cheng-Pu Chiu; Shih-Min Lu; Yung-Sung Lin - Web page: https://patentgrep.com/patent/US10373861B1 ## CPC - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates} - H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0151: {Manufacturing their isolation regions} - H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions} - H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate having a fin structure thereon; a first isolation oxide structure having a first curved top surface disposed on one side of the fin structure, wherein the first isolation oxide structure has a first uppermost edge that is in contiguous with a first sidewall of the fin structure, wherein a first angle is defined between a tangent to the first uppermost edge that contacts the first sidewall and the first sidewall, wherein the first angle is approximately 130-140 degrees; a second isolation oxide structure having a second curved top surface disposed on the other side of the fin structure opposite to the first isolation oxide structure, wherein the first isolation oxide structure and the second isolation oxide structure have different depths, wherein the second isolation oxide structure has a second uppermost edge that is in contiguous with a second sidewall of the fin structure, wherein a second angle is defined between a tangent to the second uppermost edge that contacts the second sidewall and the second side wall, and wherein the second angle is approximately 125-135 degrees; a gate disposed on the fin structure; a gate dielectric layer disposed between the plurality of fin structure and the gate; and a source/drain doped region in the fin structure. ### Claim 2 (depends on 1) The semiconductor structure according to claim 1, wherein the first uppermost edge has a first depth. ### Claim 3 (depends on 2) The semiconductor structure according to claim 2, wherein the second uppermost edge has a second depth that is greater than the first depth. ### Claim 4 (depends on 3) The semiconductor structure according to claim 3, wherein the first depth ranges between 400 and 500 angstroms and the second depth ranges between 450 and 550 angstroms. ### Claim 5 (depends on 1) The semiconductor structure according to claim 1, wherein the gate is a metal gate. ### Claim 6 (depends on 1) The semiconductor structure according to claim 1, wherein the source/drain doped region comprises an epitaxial stressor layer. ### Claim 7 A method for fabricating a semiconductor device, comprising: providing a substrate having a fin structure thereon; forming a first isolation oxide structure having a first curved top surface on one side of the fin structure, wherein the first isolation oxide structure has a first uppermost edge that is in contiguous with a first sidewall of the fin structure, wherein a first angle is defined between a tangent to the first uppermost edge that contacts the first sidewall and the first sidewall, wherein the first angle is approximately 130-140 degrees; forming a second isolation oxide structure having a second curved top surface on the other side of the fin structure opposite to the first isolation oxide structure, wherein the first isolation oxide structure and the second isolation oxide structure have different depths, wherein the second isolation oxide structure has a second uppermost edge that is in contiguous with a second sidewall of the fin structure, wherein a second angle is defined between a tangent to the second uppermost edge that contacts the second sidewall and the second side wall, and wherein the second angle is approximately 125-135 degrees; forming a gate disposed on the fin structure; and forming a source/drain doped region in the fin structure. ### Claim 8 (depends on 7) The method for fabricating a semiconductor device according to claim 7, wherein the first uppermost edge has a first depth. ### Claim 9 (depends on 8) The method for fabricating a semiconductor device according to claim 8, wherein the second uppermost edge has a second depth that is greater than the first depth. ### Claim 10 (depends on 9) The method for fabricating a semiconductor device according to claim 9, wherein the first depth ranges between 400 and 500 angstroms and the second depth ranges between 450 and 550 angstroms. ### Claim 11 (depends on 7) The method for fabricating a semiconductor device according to claim 7, wherein the source/drain doped region comprises an epitaxial stressor layer.