# US 10,373,843 B2 · Display device and method for manufacturing the same

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- Number: US 10,373,843 B2
- Document ID: US10373843B2
- Status: Granted
- Kind: B2
- Application number: 14/790,668
- Filed: 2015-07-02
- Published: 2015-10-22
- Granted: 2019-08-06
- Earliest claimed: 2009-08-27
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Junichiro Sakata; Masashi Tsubuku; Kengo Akimoto; Miyuki Hosoba; Masayuki Sakakura; Yoshiaki Oikawa
- Web page: https://patentgrep.com/patent/US10373843B2

## CPC

- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/0229: {characterised by control of the annealing or irradiation parameters}
- H10D 86/0251: {characterised by increasing the uniformity of device parameters}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/38: {characterised by treatments done after the formation of the materials}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer;
performing a first heat treatment on the oxide semiconductor layer;
forming a source electrode layer and a drain electrode layer after performing the first heat treatment, wherein the source electrode layer is formed over and in contact with a first region of the oxide semiconductor layer and the drain electrode layer is formed over and in contact with a second region of the oxide semiconductor layer;
forming an inorganic insulating layer over and in contact with a third region of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer so that a resistance of the third region of the oxide semiconductor layer is increased; and
performing a second heat treatment after forming the inorganic insulating layer,
wherein the third region of the oxide semiconductor layer is between the first region of the oxide semiconductor layer and the second region of the oxide semiconductor layer, and
wherein a conductivity of the third region of the oxide semiconductor layer is lower than a conductivity of each of the first region and the second region of the oxide semiconductor layer.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment on the oxide semiconductor layer is performed under an atmosphere including nitrogen.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment on the oxide semiconductor layer is performed at a temperature higher than or equal to 400° C.

### Claim 4 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the second heat treatment is performed on the inorganic insulating layer so that oxygen in the inorganic insulating layer is supplied to the third region of the oxide semiconductor layer.

### Claim 5 (depends on 4)

The method for manufacturing a semiconductor device according to claim 4, wherein the second heat treatment on the inorganic insulating layer is performed under an atmosphere including nitrogen.

### Claim 6 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a crystal.

### Claim 7 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer is a stacked film.

### Claim 8 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

### Claim 9 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, tin, and zinc.