# US 10,373,837 B2 · Memory device

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- Number: US 10,373,837 B2
- Document ID: US10373837B2
- Status: Granted
- Kind: B2
- Application number: 15/705,014
- Filed: 2017-09-14
- Published: 2018-01-04
- Granted: 2019-08-06
- Earliest claimed: 2015-08-24
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Kun-Huang Yu; Shih-Yin Hsiao
- Web page: https://patentgrep.com/patent/US10373837B2

## CPC

- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/44: with a control gate layer also being used as part of the peripheral transistor
- H10B 41/46: with an inter-gate dielectric layer also being used as part of the peripheral transistor
- H10D 30/6894: {having one gate at least partly in a trench}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

## Claims

### Claim 1

A memory device, comprising:
a first gate, buried in a substrate;
a second gate, disposed on the substrate, wherein the second gate comprises metal;
an inter-gate dielectric layer, disposed between the first gate and the second gate, wherein the inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10, and an interfacial layer disposed between the high-k layer and the first gate; and
a spacer, disposed on and in physical contact with sidewalls of the second gate,
a tunnel insulating layer disposed between the first gate and the substrate,
wherein a bottommost surface of the spacer is coplanar with a bottommost surface of the interfacial layer of the inter-gate dielectric layer, and a portion of the tunnel insulating layer further extends into the interfacial layer of the inter-gate dielectric layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein a dimension of the second gate is greater than a dimension of the first gate, and the inter-gate dielectric layer is further disposed between the second gate and the substrate.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising at least two doped regions disposed in the substrate beside the first gate.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein a depth of the first gate is greater than a depth of the doped regions.

### Claim 5 (depends on 1)

The memory device of claim 1, further comprising a third gate disposed on the substrate, wherein the third gate comprises metal.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the substrate has a cell area and a MOS device area.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first gate and the second gate are disposed in the cell area, and the third gate is disposed in the MOS device area.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein an upper surface of the second gate and an upper surface of the third gate are coplanar, and a bottom surface of the second gate and a bottom surface of the third gate are coplanar.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein a top surface of the portion of the tunnel insulating layer is covered by the high-k layer of the inter-gate dielectric layer.