# US 10,373,834 B2 · Method for manufacturing a metal gate

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- Number: US 10,373,834 B2
- Document ID: US10373834B2
- Status: Granted
- Kind: B2
- Application number: 15/944,800
- Filed: 2018-04-04
- Published: 2019-06-20
- Granted: 2019-08-06
- Earliest claimed: 2017-12-20
- Assignees: Shaghai Huali Microelectronics Corporation
- Applicants: Shanghai Huali Microelectronics Corporation
- Inventors: Qiuming Huang
- Web page: https://patentgrep.com/patent/US10373834B2

## CPC

- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides a semiconductor structure of a metal gate and a manufacturing method therefor. The manufacturing method includes providing a semiconductor substrate; uniformly depositing a first hard mask layer on the semiconductor substrate, corresponding to a region where the metal gate is located, patterning and etching the first hard mask layer to form a recess, forming a sloping sidewall on a sidewall of the recess, the sloping sidewall and an upper surface of the substrate forming a groove structure, with the size of an upper part of the groove structure being larger than that of a lower part thereof, and forming a metal gate in the groove structure; and removing the first hard mask layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, the method comprising:
providing a semiconductor substrate;
uniformly depositing a first hard mask layer on the semiconductor substrate;
corresponding to a region where a first metal gate is located, patterning and etching the first hard mask layer to form a recess;
forming a sloping sidewall on a sidewall of the recess, the sloping sidewall and an upper surface of the substrate forming a groove structure, wherein a size of an upper part of the groove structure being larger than a lower part;
forming a second metal gate in the groove structure, wherein the forming of the second metal gate further comprises:
depositing a polysilicon layer on the upper surface of the first hard mask layer and in the groove structure;
planarizing the polysilicon layer to remove polysilicon from the upper surface of the first hard mask layer to form a dummy gate in the groove structure;
depositing a second hard mask layer on the upper surfaces of the first hard mask layer and the dummy gate;
corresponding to a region other than the side wall and the dummy gate, patterning and etching the second hard mask layer and the first hard mask layer, and reserving the sidewall, the dummy gate and the second hard mask layer covering the upper surface of the dummy gate;
depositing a dielectric layer on the semiconductor substrate to cover the semiconductor substrate and the upper surface of the second hard mask layer;
planarizing the dielectric layer, and removing the second hard mask layer covering the upper surface of the dummy gate, such that an upper surface of the dielectric layer is flush with the upper surface of the dummy gate; and
removing the dummy gate and depositing a third metal gate in the groove structure; and
removing the first hard mask layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the sloping sidewall on the sidewall of the recess comprises:
uniformly depositing a dielectric medium on an upper surface of the first hard mask layer and the sidewall and the bottom of the recess;
etching the dielectric medium covering the upper surface of the first hard mask layer and the bottom of the recess; and
reserving the dielectric medium covering the sidewall of the recess to form the sloping sidewall.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
before depositing the dielectric layer, performing ion implantation in a source region and a drain region on two sides of the dummy gate to form lightly doped drain structures.

### Claim 4 (depends on 1)

The method of claim 1, wherein material of the sidewall is the same material as the dielectric layer.