# US 10,373,833 B2 · Semiconductor device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,833 B2 - Document ID: US10373833B2 - Status: Granted - Kind: B2 - Application number: 15/056,013 - Filed: 2016-02-29 - Published: 2016-09-29 - Granted: 2019-08-06 - Earliest claimed: 2015-03-24 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Aya Shindome; Masahiko Kuraguchi; Hisashi Saito; Shigeto Fukatsu; Miki Yumoto; Yosuke Kajiwara - Web page: https://patentgrep.com/patent/US10373833B2 ## CPC - H10P 30/206: {into Group III-V semiconductors} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10P 30/208: {of electrically inactive species} - H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices - H10W 10/01: {Manufacture or treatment} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess. ## Claims ### Claim 1 A semiconductor device comprising: a first GaN-based semiconductor layer; a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer, the second GaN-based semiconductor layer having a larger bandgap than the first GaN-based semiconductor layer; a source electrode provided on the second GaN-based semiconductor layer; a drain electrode provided on the second GaN-based semiconductor layer; a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer; a gate insulating film provided on a surface of the recess; and a gate electrode provided on the gate insulating film, the gate electrode having an end portion in a gate width direction, located in the recess, wherein a first distance between the gate electrode and the bottom of the recess is shorter than a second distance between an end portion of the gate electrode in the gate width direction and a side surface of the recess, a length of the gate electrode in a gate width direction is larger than a length of the gate electrode in a gate length direction, a length of the recess in the gate width direction is larger than a length of the recess in the gate length direction, and the length of the recess in the gate width direction is larger than the length of the gate electrode in the gate width direction. ### Claim 2 (depends on 1) The device according to claim 1, wherein a length of the recess in a gate length direction at an end portion of the recess in the gate width direction is longer than a length of the gate electrode in the gate length direction at the end portion of the gate electrode in the gate width direction. ### Claim 3 (depends on 1) The device according to claim 1, wherein a length of the recess in a gate length direction at a central portion of the recess in the gate width direction is shorter than a length of the gate electrode in the gate length direction at a central portion of the gate electrode in the gate width direction. ### Claim 4 (depends on 1) The device according to claim 1, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, wherein an end portion of the recess in the gate width direction and the end portion of the gate electrode in the gate width direction are on the device isolation region. ### Claim 5 (depends on 1) The device according to claim 1, wherein a bottom of the recess is located in the first GaN-based semiconductor layer. ### Claim 6 (depends on 1) The device according to claim 1, wherein a bottom of the recess is located in the second GaN-based semiconductor layer and a distance between the bottom of the recess and the first GaN-based semiconductor layer is 5 nm or less. ### Claim 7 (depends on 1) The device according to claim 1, wherein the length of the recess in the gate length direction at the end portion of the recess in the gate width direction is longer than the length of the gate electrode in the gate length direction at a central portion of the gate electrode in the gate width direction, and the length of the gate electrode in the gate length direction at the end portion of the gate electrode in the gate width direction is longer than the length of the recess in a gate length direction at a central portion of the recess in the gate width direction. ### Claim 8 A semiconductor device comprising: a first GaN-based semiconductor layer; a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer, the second GaN-based semiconductor layer having a larger bandgap than the first GaN-based semiconductor layer; a source electrode provided on the second GaN-based semiconductor layer; a drain electrode provided on the second GaN-based semiconductor layer; a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer; a gate insulating film provided on a surface of the recess; and a gate electrode provided on the gate insulating film, located in the recess, wherein a length of the gate electrode in a gate width direction is larger than a length of the gate electrode in a gate length direction, a length of the recess in the gate width direction is larger than a length of the recess in the gate length direction, and the length of the recess in the gate width direction is larger than the length of the gate electrode in the gate width direction. ### Claim 9 (depends on 8) The device according to claim 8, wherein the length of the recess in the gate length direction at an end portion of the recess in the gate width direction is longer than the length of the gate electrode in the gate length direction at an end portion of the gate electrode in the gate width direction. ### Claim 10 (depends on 8) The device according to claim 8, wherein the length of the recess in the gate length direction at a central portion of the recess in the gate width direction is shorter than the length of the gate electrode in the gate length direction at a central portion of the gate electrode in the gate width direction. ### Claim 11 (depends on 8) The device according to claim 8, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, wherein an end portion of the recess in the gate width direction and the end portion of the gate electrode in the gate width direction are on the device isolation region. ### Claim 12 (depends on 8) The device according to claim 8, wherein the length of the recess in the gate length direction at the end portion of the recess in the gate width direction is longer than the length of the gate electrode in the gate length direction at a central portion of the gate electrode in the gate width direction, and the length of the gate electrode in the gate length direction at the end portion of the gate electrode in the gate width direction is longer than the length of the recess in the gate length direction at a central portion of the recess in the gate width direction. ### Claim 13 A semiconductor device comprising: a first GaN-based semiconductor layer; a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer, the second GaN-based semiconductor layer having a larger bandgap than the first GaN-based semiconductor layer; a source electrode provided on the second GaN-based semiconductor layer; a drain electrode provided on the second GaN-based semiconductor layer; a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer; a gate insulating film provided on a surface of the recess; and a gate electrode provided on the gate insulating film, located in the recess, wherein a length of the recess in a gate width direction is larger than a length of the gate electrode in the gate width direction, and the length of the recess in a gate length direction at an end portion of the recess in the gate width direction is longer than the length of the gate electrode in the gate length direction at an end portion of the gate electrode in the gate width direction. ### Claim 14 A semiconductor device comprising: a first GaN-based semiconductor layer; a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer, the second GaN-based semiconductor layer having a larger bandgap than the first GaN-based semiconductor layer; a source electrode provided on the second GaN-based semiconductor layer; a drain electrode provided on the second GaN-based semiconductor layer; a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer; a gate insulating film provided on a surface of the recess; and a gate electrode provided on the gate insulating film, the gate electrode having an end portion in a gate width direction, located in the recess, wherein a first distance between the gate electrode and the bottom of the recess is shorter than a second distance between an end portion of the gate electrode in the gate width direction and a side surface of the recess, the gate length direction is parallel to a direction in which a current of the transistor flows, and the gate width direction is perpendicular to the gate length direction. ### Claim 15 (depends on 14) The device according to claim 14, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, wherein an end portion of the recess in the gate width direction and the end portion of the gate electrode in the gate width direction are on the device isolation region. ### Claim 16 (depends on 15) The device according to claim 15, wherein the device isolation region is formed by implantation of at least one kind of ion selected from argon (Ar), nitrogen (N), boron (B), and phosphorus (P) into the first GaN-based semiconductor layer and the second GaN-based semiconductor layer. ### Claim 17 A semiconductor device comprising: a first GaN-based semiconductor layer; a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer, the second GaN-based semiconductor layer having a larger bandgap than the first GaN-based semiconductor layer; a source electrode provided on the second GaN-based semiconductor layer; a drain electrode provided on the second GaN-based semiconductor layer; a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer; a gate insulating film provided on a surface of the recess; and a gate electrode provided on the gate insulating film, located in the recess, wherein a length of the gate electrode in a gate width direction is larger than a length of the gate electrode in a gate length direction, a length of the recess in the gate width direction is larger than a length of the recess in the gate length direction, the length of the recess in the gate width direction is larger than the length of the gate electrode in the gate width direction, the gate length direction is parallel to a direction in which a current of the transistor flows, and the gate width direction is perpendicular to the gate length direction. ### Claim 18 (depends on 17) The device according to claim 17, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, wherein an end portion of the recess in the gate width direction and the end portion of the gate electrode in the gate width direction are on the device isolation region. ### Claim 19 (depends on 18) The device according to claim 18, wherein the device isolation region is formed by implantation of at least one kind of ion selected from argon (Ar), nitrogen (N), boron (B), and phosphorus (P) into the first GaN-based semiconductor layer and the second GaN-based semiconductor layer. ### Claim 20 (depends on 1) The device according to claim 1, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, a boundary being provided between the first GaN-based semiconductor layer and the first the device isolation region, wherein an end portion of the recess in the gate width direction is on the device isolation region, and a side surface of the end portion of the gate electrode in the gate width direction is right on the boundary. ### Claim 21 (depends on 8) The device according to claim 8, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, a boundary being provided between the first GaN-based semiconductor layer and the first the device isolation region, wherein an end portion of the recess in the gate width direction is on the device isolation region, and a side surface of the end portion of the gate electrode in the gate width direction is right on the boundary. ### Claim 22 (depends on 13) The device according to claim 13, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, a boundary being provided between the first GaN-based semiconductor layer and the first the device isolation region, wherein an end portion of the recess in the gate width direction is on the device isolation region, and a side surface of the end portion of the gate electrode in the gate width direction is right on the boundary. ### Claim 23 (depends on 14) The device according to claim 14, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, a boundary being provided between the first GaN-based semiconductor layer and the first the device isolation region, wherein an end portion of the recess in the gate width direction is on the device isolation region, and a side surface of the end portion of the gate electrode in the gate width direction is right on the boundary. ### Claim 24 (depends on 17) The device according to claim 17, further comprising a device isolation region provided in the first GaN-based semiconductor layer and the second GaN-based semiconductor layer, a boundary being provided between the first GaN-based semiconductor layer and the first the device isolation region, wherein an end portion of the recess in the gate width direction is on the device isolation region, and a side surface of the end portion of the gate electrode in the gate width direction is right on the boundary.