# US 10,373,832 B2 · Dynamic random access memory with low leakage current and related manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,832 B2 - Document ID: US10373832B2 - Status: Granted - Kind: B2 - Application number: 15/672,270 - Filed: 2017-08-08 - Published: 2018-02-08 - Granted: 2019-08-06 - Earliest claimed: 2016-08-08 - Assignees: Etron Technology, Inc. - Applicants: Etron Technology, Inc. - Inventors: Li-Ping Huang - Web page: https://patentgrep.com/patent/US10373832B2 ## CPC - H10P 30/21: {of electrically active species} - H10B 12/05: {Making the transistor} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10B 12/485: {Bit line contacts} - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes} - H10D 64/027: {by etching at gate locations} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 30/204: {into Group IV semiconductors} - H10P 30/221: {characterised by the angle between the ion beam and the mask} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - H10P 30/206: {into Group III-V semiconductors} - H10P 30/212: {Through-implantation} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A manufacturing method of dynamic random access memory (DRAM) with low leakage current includes forming a plurality of gates within a substrate of the DRAM; forming a plurality of drain/sources within the substrate of the DRAM by a first ion implantation; and forming a plurality of lightly doped drains under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation after the plurality of drain/sources are formed. The plurality of lightly doped drains is used for reducing a leakage current within the DRAM, and the second ion implantation has a predetermined incident angle. ## Claims ### Claim 1 A manufacturing method of a dynamic random access memory with low leakage current, comprising: forming a plurality of gates of the dynamic random access memory within a substrate of the dynamic random access memory; forming a plurality of drain/sources of the dynamic random access memory within the substrate by a first ion implantation; and forming a plurality of lightly doped drains under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation after the plurality of drain/sources are formed, wherein the plurality of lightly doped drains is used for reducing a leakage current within the dynamic random access memory, and the second ion implantation has a predetermined incident angle; wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain. ### Claim 2 (depends on 1) The manufacturing method of claim 1, wherein concentration of the second ion implantation is lower than concentration of the first ion implantation. ### Claim 3 (depends on 1) The manufacturing method of claim 1, wherein the substrate has a first conductivity type, the first ion implantation and the second ion implantation have a second conductivity type, and the first conductivity type is opposite to the second conductivity type. ### Claim 4 (depends on 1) The manufacturing method of claim 1, wherein the plurality of gates act as bit lines of the dynamic random access memory. ### Claim 5 (depends on 1) The manufacturing method of claim 1, wherein ion species corresponding to the second ion implantation is arsenic, phosphorus, phosphorus plus carbon, arsenic plus phosphorus plus carbon, or germanium plus phosphorus plus carbon. ### Claim 6 (depends on 1) The manufacturing method of claim 1, wherein the predetermined incident angle is an angle within 7°˜45°. ### Claim 7 (depends on 1) The manufacturing method of claim 1, wherein the plurality of gates are metal gates composed of tungsten. ### Claim 8 (depends on 1) The manufacturing method of claim 1, wherein an incident direction of the second ion implantation is rotatable. ### Claim 9 (depends on 1) The manufacturing method of claim 1, wherein concentration of the second ion implantation is between 1E13/cm2 and 2E15/cm2. ### Claim 10 A dynamic random access memory with low leakage current, comprising: a substrate; a plurality of gates formed within the substrate; a plurality of drain/sources, wherein the plurality of drain/sources are formed within the substrate by a first ion implantation; and a plurality of lightly doped drains, wherein the plurality of lightly doped drains are formed under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation, wherein the plurality of lightly doped drains is used for reducing a leakage current within the dynamic random access memory, and the second ion implantation has a predetermined incident angle; wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain. ### Claim 11 (depends on 10) The dynamic random access memory of claim 10, wherein concentration of the second ion implantation is lower than concentration of the first ion implantation. ### Claim 12 (depends on 10) The dynamic random access memory of claim 10, wherein the substrate has a first conductivity type, the first ion implantation and the second ion implantation have a second conductivity type, and the first conductivity type is opposite to the second conductivity type. ### Claim 13 (depends on 10) The dynamic random access memory of claim 10, wherein the plurality of gates act as bit lines of the dynamic random access memory. ### Claim 14 (depends on 10) The dynamic random access memory of claim 10, wherein ion species corresponding to the second ion implantation is arsenic, phosphorus, phosphorus plus carbon, arsenic plus phosphorus plus carbon, or germanium plus phosphorus plus carbon. ### Claim 15 (depends on 10) The dynamic random access memory of claim 10, wherein the predetermined incident angle is an angle within 7°˜45°. ### Claim 16 (depends on 10) The dynamic random access memory of claim 10, wherein the plurality of gates are metal gates composed of tungsten. ### Claim 17 (depends on 10) The dynamic random access memory of claim 10, wherein each gate of the plurality of gates and an adjacent gate thereof share the corresponding drain/source. ### Claim 18 (depends on 10) The dynamic random access memory of claim 10, wherein an incident direction of the second ion implantation is rotatable. ### Claim 19 (depends on 10) The dynamic random access memory of claim 10, wherein concentration of the second ion implantation is between 1E13/cm2 and 2E15/cm2. ### Claim 20 A dynamic random access memory with low leakage current, comprising: a substrate; a plurality of gates formed within the substrate; a plurality of drain/sources, wherein the plurality of drain/sources are formed within the substrate by a first ion implantation; and a plurality of lightly doped drains, wherein the plurality of lightly doped drains are formed under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation, wherein the plurality of lightly doped drains is used for reducing a leakage current within the dynamic random access memory, an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain. ### Claim 21 A dynamic random access memory with low leakage current, comprising: a substrate; a plurality of gates formed within the substrate; a plurality of drain/sources formed within the substrate; and a plurality of lightly doped drains, wherein lightly doped drains are formed on side walls of two adjacent gates, and the lightly doped drains are under corresponding drain/sources; wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain. ### Claim 22 A dynamic random access memory with low leakage current, comprising: a substrate; a plurality of gates formed within the substrate; a plurality of drain/sources formed within the substrate; a plurality of isolation layers formed within the substrate, and each isolation layer is located between two gates; and a plurality of lightly doped drains, wherein lightly doped drains are formed on side walls of the two gates facing the each isolation layer and side walls of the each isolation layer, and the lightly doped drains are under corresponding drain/sources; wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of the a corresponding drain/source on the each lightly doped drain.