# US 10,373,759 B1 · Multilayer ceramic electronic component having external electrodes with holes in plating layers

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- Number: US 10,373,759 B1
- Document ID: US10373759B1
- Status: Granted
- Kind: B1
- Application number: 16/186,008
- Filed: 2018-11-09
- Granted: 2019-08-06
- Earliest claimed: 2018-09-05
- Assignees: Samsung Electro-Mechanics Co., Ltd.
- Applicants: Samsung Electro-Mechanics Co., Ltd.
- Inventors: Hye Young Choi; Jong Ho Lee; Eui Hyun Jo; Jang Yeol Lee; Jin Woo Lee; Hyun Hee Gu
- Web page: https://patentgrep.com/patent/US10373759B1

## CPC

- H01G 2/065: {for surface mounting, e.g. chip capacitors}
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H05K 1/181: associated with surface mounted components
- H05K 2201/10015: Non-printed capacitor
- H05K 2201/10636: Leadless chip, e.g. chip capacitor or resistor
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A multilayer ceramic electronic component includes a ceramic body including dielectric layers and first and second internal electrodes alternately stacked with each of the dielectric layers interposed therebetween. First and second external electrodes are disposed on outer surfaces of the ceramic body, connected to the first and second internal electrodes respectively, and disposed to cover at least five of eight corners of the ceramic body. The first and second external electrodes include, respectively, first and second base electrode layers at least partially in contact with the outer surfaces of the ceramic body and first and second plating layers disposed to cover the first and second base electrode layers, respectively. The first and second plating or base electrode layers have one or more to three or less holes positioned adjacent to one or more to three or less of the eight corners of the ceramic body.

## Claims

### Claim 1

A multilayer ceramic electronic component comprising:
a ceramic body including dielectric layers and first and second internal electrodes alternately stacked in a thickness direction and respectively exposed to opposing end surfaces of the ceramic body with each of the dielectric layers interposed therebetween; and
first and second external electrodes disposed on outer surfaces of the ceramic body to be connected to the first and second internal electrodes, respectively, and disposed to cover at least five of eight corners of the ceramic body,
wherein the first and second external electrodes include, respectively, first and second base electrode layers at least partially in contact with the outer surfaces of the ceramic body and first and second plating layers disposed to cover the first and second base electrode layers, respectively, and
the first and second plating layers have one or more to three or less holes positioned adjacent to one or more to three or less of the eight corners of the ceramic body.

### Claim 2 (depends on 1)

The multilayer ceramic electronic component of claim 1,
wherein each of the first and second internal electrodes extends in a plane extending in width and length directions, and a thickness of each of the first and second external electrodes at a center of a [width×thickness] surface is 10 μm or less.

### Claim 3 (depends on 2)

The multilayer ceramic electronic component of claim 2, wherein the first and second external electrodes further include, respectively, first and second conductive resin layers disposed between the first and second base electrode layers and the first and second plating layers, respectively, and
at least one of the first and second conductive resin layers is exposed through the holes in the first and second plating layers.

### Claim 4 (depends on 3)

The multilayer ceramic electronic component of claim 3, wherein the first and second external electrodes further include, respectively, first and second tin plating layers disposed on outer surfaces of the first and second plating layers, respectively, and each of the first and second plating layers contains nickel.

### Claim 5 (depends on 4)

The multilayer ceramic electronic component of claim 4, wherein the first and second tin plating layers cover the holes in the first and second plating layers, respectively.

### Claim 6 (depends on 5)

The multilayer ceramic electronic component of claim 5, wherein a thickness of each of the first and second plating layers at a center of a [width×thickness] surface is 3 μm or more to 5 μm or less.

### Claim 7 (depends on 2)

The multilayer ceramic electronic component of claim 2,
wherein the first and second base electrode layers have one or more to three or less holes each positioned adjacent to the holes in the first and second plating layers.

### Claim 8 (depends on 7)

The multilayer ceramic electronic component of claim 7, wherein the first and second external electrodes further include, respectively, first and second conductive resin layers disposed between the first and second base electrode layers and the first and second plating layers, respectively, and
the first and second conductive resin layers have one or more to three or less holes each positioned adjacent to the holes in the first and second plating layers.

### Claim 9 (depends on 8)

The multilayer ceramic electronic component of claim 8, wherein a thickness of each of the first and second plating layers at a center of a [width×thickness] surface is 3 μm or more to 5 μm or less.

### Claim 10 (depends on 9)

The multilayer ceramic electronic component of claim 9, wherein an average thickness of each dielectric layer disposed between adjacent first and second internal electrodes is 0.4 μm or less, and
an average thickness of each of the first and second internal electrodes is 0.4 μm or less.

### Claim 11 (depends on 10)

The multilayer ceramic electronic component of claim 10, further comprising first and second solders connected to the first and second external electrodes, respectively, on a board.
