# US 10,373,698 B1 · Electronic device with a fuse array mechanism > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,698 B1 - Document ID: US10373698B1 - Status: Granted - Kind: B1 - Application number: 15/967,022 - Filed: 2018-04-30 - Granted: 2019-08-06 - Earliest claimed: 2018-04-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: John E. Riley; Girish N. Cherussery; Scott E. Smith; Yu-Feng Chen - Web page: https://patentgrep.com/patent/US10373698B1 ## CPC - G11C 17/16: using electrically-fusible links - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 11/34: using semiconductor devices - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 29/787: {using a fuse hierarchy} - H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel. ## Claims ### Claim 1 An electronic device, comprising: a fuse array including fuse cells organized along a first direction and a second direction, wherein: each fuse cell includes: a fuse element configured to store information, and a first selection element directly connected to the fuse element and configured to provide access to the fuse element according to a position of the fuse cell element along the first direction; and the fuse array includes a second selection element directly connected to the first selection element, the second selection element configured to provide access to the fuse element according to a position of the fuse cell element along the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from two or more of the fuse cells in parallel, wherein the fuse read output represents a single value that corresponds to the two or more of the fuse cells. ### Claim 2 (depends on 1) The electronic device of claim 1, wherein the first selection element is a MOSFET device. ### Claim 3 (depends on 2) The electronic device of claim 2, wherein the first selection element is an N-channel MOSFET device including: a drain portion directly connected to the fuse element; a gate portion configured to receive a first selection signal for operating the N-channel MOSFET device; and a source portion directly connected to the second selection element. ### Claim 4 (depends on 1) The electronic device of claim 1, wherein the second selection element is an NMOS device. ### Claim 5 (depends on 4) The electronic device of claim 4, wherein the NMOS device includes: a drain portion directly connected to the first selection element; a gate portion configured to receive a second selection signal for operating the NMOS device; and a source portion directly connected to the fuse read circuit. ### Claim 6 (depends on 1) The electronic device of claim 1, further comprising a fuse write element coupled to the fuse element and the selection circuit, the fuse write element configured to write/program the fuse element. ### Claim 7 (depends on 1) The electronic device of claim 1, wherein the fuse element is a transistor device including: a first portion directly connected to electrical ground; a gate portion configured to receive a fuse write select; and a second portion directly connected to the selection circuit, wherein: the fuse element is directly connected to the selection circuit and directly connected to a conditional ground opposite the selection circuit, wherein the conditional ground and the fuse write select is configured to driven above a device ground to write/program the fuse element. ### Claim 8 (depends on 1) The electronic device of claim 1, wherein the fuse array includes a first fuse cell configured to store information and at least one redundant fuse configured to store the same information. ### Claim 9 (depends on 8) The electronic device of claim 8, wherein the fuse read circuit includes an output latch circuit configured to store a latched output resulting from reading the first fuse cell while reading the at least one redundant fuse. ### Claim 10 (depends on 1) The electronic device of claim 1, further comprising one or more fuse sets that each include multiple arrays and multiple read circuits, wherein each of the arrays are coupled to at least one read circuit. ### Claim 11 (depends on 10) The electronic device of claim 10, wherein the multiple arrays and the multiple read circuits are grouped into segment groupings within each of the fuse sets. ### Claim 12 (depends on 11) The electronic device of claim 11, wherein each fuse set is configured to select a particular array based on a grouping selection signal and a segment address signal, wherein the grouping selection signal is for selecting one of the segment groupings within the fuse set and the segment address signal is for selecting one of the arrays within the selected segment grouping. ### Claim 13 (depends on 1) The electronic device of claim 1, wherein: the fuse array includes the fuse cells connected together at a fuse read node; and the fuse read circuit is connected to the fuse read node. ### Claim 14 (depends on 1) The electronic device of claim 1, wherein the fuse element includes an anti-fuse including an oxide layer for representing an unblown setting or a blown setting, wherein the unblown setting corresponds to a first resistance level associated with an electrical open and the blown setting corresponds to a second resistance level associated with an electrical short, the second resistance level lower than the first resistance level. ### Claim 15 A method of operating an electronic device including a fuse array including multiple fuse cells, comprising: generating a first selection signal for identifying a fuse cell along a first direction; generating a second selection signal for identifying the fuse cell along a second direction; and providing access to the fuse cell based on: operating a second selection element according to the second selection signal, and operating a first selection element according to the first selection signal to directly connect the fuse cell to the second selection element. ### Claim 16 (depends on 15) The method of claim 15, wherein providing access to the fuse cell includes connecting a fuse element in the fuse cell to a fuse read circuit through the first selection element and the second selection element. ### Claim 17 (depends on 15) The method of claim 15, wherein: providing access to the fuse cell includes connecting a fuse element in the fuse cell to a write voltage through the first selection element, the second selection element, and a fuse write element; and further comprising: driving a conditional ground above a device ground to program the connected fuse element, wherein the conditional ground is connected to the fuse element opposite the first selection element. ### Claim 18 A method of manufacturing an electronic device, comprising: providing a fuse array including fuse cells organized along a first direction and a second direction, wherein: each fuse cell includes: a fuse element configured to store information, and a first selection element directly connected to the fuse element and configured to provide access to the fuse element according to a position of the fuse cell element along the first direction; and the fuse array includes a second selection element directly connected to the first selection element, the second selection element configured to provide access to the fuse element according to a position of the fuse cell element along the second direction; and connecting a fuse read circuit to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells. ### Claim 19 (depends on 18) The method of claim 18, wherein providing the fuse array includes forming the fuse cell based on: providing the first selection element connected to a fuse write element; and connecting the second selection circuit to the first selection element.