# US 10,373,689 B2 · Semiconductor memory device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,689 B2 - Document ID: US10373689B2 - Status: Granted - Kind: B2 - Application number: 15/641,485 - Filed: 2017-07-05 - Published: 2018-05-10 - Granted: 2019-08-06 - Earliest claimed: 2016-11-10 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Dong Hun Lee - Web page: https://patentgrep.com/patent/US10373689B2 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform an erase operation on a selected memory block. The control circuit may control the peripheral circuit such that, during the erase operation, when the selected memory block has passed an erase verification, an additional erase verification operation is performed on memory cells coupled to a reference word line among a plurality of word lines coupled to the selected memory block, and the erase operation is performed according to a result of the additional erase verification operation for the memory cells coupled to the reference word line. ## Claims ### Claim 1 A semiconductor memory device comprising: a plurality of memory cells included in a plurality of memory blocks, respectively; a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit to perform an additional erase verification operation, when threshold voltages of all memory cells included in the selected memory block have reached an erase state, on memory cells coupled to a reference word line among a plurality of word lines coupled to the selected memory block, and to perform an additional erase operation according to a result of the additional erase verification operation for the memory cells coupled to the reference word line included in the selected memory block, wherein the control circuit is configured to designate a word line to be selected first to be the reference word line according to a predetermine program sequence, and wherein the additional erase verification operation is performed on less than all of the plurality of word lines. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein, during the erase operation, the control circuit repeatedly performs, until the threshold voltages of all memory cells included in the selected memory block have reached the erase state, an erase voltage application operation of applying an erase voltage to the selected memory block, and an erase verification operation for the selected memory block. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein, each time the erase voltage application operation and the erase verification operation are repeatedly performed, the control circuit increases the erase voltage by a first step voltage. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the control circuit increases the erase voltage by a second step voltage having a level less than a level of the first step voltage when the memory cells coupled to the reference word line have failed the additional erase verification operation. ### Claim 5 (depends on 2) The semiconductor memory device according to claim 2, wherein, each time the erase voltage application operation and the erase verification operation are repeatedly performed, the control circuit applies the erase voltage to the selected memory block for a duration of a first time. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein the control circuit applies the erase voltage to the selected memory block for a duration of a second time shorter than the first time when the memory cells coupled to the reference word line have failed the additional erase verification operation. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein, when the memory cells coupled to the reference word line have passed the additional erase verification operation, the control circuit terminates the erase operation. ### Claim 8 A method of operating a semiconductor memory device, comprising: performing an erase operation on a plurality of memory cells included in a selected memory block among a plurality of memory blocks using a first step voltage; performing a first verify operation using a first verify voltage to check whether an erase operation of the selected memory block has been completed; performing a second verify operation according to a result of the first verify operation to check whether threshold voltages of memory cells coupled to a reference word line have reached the first verify voltage; and performing an additional erase operation on the plurality of memory cells included in the selected memory block using an erase condition determine by a result of the second verify operation, wherein the reference word line is a word line of a plurality of word lines which is designated to be selected first according to a predetermine program sequence of the selected memory block, and wherein the second verify operation is performed on less than all of the plurality of word lines. ### Claim 9 (depends on 8) The method according to claim 8, wherein the performing the second verify operation comprises: verifying the threshold voltages of the memory cells coupled to the reference word line among a plurality of word lines coupled to the selected memory block to check whether the threshold voltages have reached the first verify voltage when the selected memory block has passed the first verify operation. ### Claim 10 (depends on 9) The method according to claim 9, wherein the performing the additional erase operation comprises: performing the erase operation on the plurality of memory cells included in the selected memory block among the plurality of memory blocks using a second step voltage less than the first step voltage when the second verify operation has failed. ### Claim 11 (depends on 8) The method according to claim 8, wherein the performing the second verify operation comprises: verifying threshold voltages of the plurality of memory cells included in the selected memory block to check whether the threshold voltages have reached a second verify voltage having a level higher than a level of the first verify voltage. ### Claim 12 (depends on 11) The method according to claim 11, wherein the performing the additional erase operation comprises: performing the erase operation on the plurality of memory cells included in the selected memory block among the plurality of memory blocks using a third step voltage less than the first step voltage when the second verify operation has passed. ### Claim 13 (depends on 11) The method according to claim 11, wherein the performing the additional erase operation comprises: performing the erase operation on the plurality of memory cells included in the selected memory block among the plurality of memory blocks using a fourth step voltage higher than the first step voltage when the second verify operation has failed. ### Claim 14 A method of operating a semiconductor memory device, comprising: performing an erase operation on a plurality of memory cells included in a selected memory block among a plurality of memory blocks using a first duration time of an erase voltage; performing a first verify operation using a first verify voltage to check whether an erase operation of the selected memory block has been completed; performing a second verify operation according to a result of the first verify operation to check whether threshold voltages of memory cells coupled to a reference word line have reached the first verify voltage; and performing an additional erase operation on the plurality of memory cells included in the selected memory block using an erase condition determine by a result of the second verify operation, wherein the reference word line is a word line of a plurality of word lines which is designated to be selected first according to a predetermine program sequence of the selected memory block, and wherein the second verify operation is performed on less than all of the plurality of word lines. ### Claim 15 (depends on 14) The method according to claim 14, wherein the performing the second verify operation comprises: verifying the threshold voltages of the memory cells coupled to the reference word line among a plurality of word lines coupled to the selected memory block to check whether the threshold voltages have reached the first verify voltage when the selected memory block has passed the first verify operation. ### Claim 16 (depends on 15) The method according to claim 15, wherein the performing the additional erase operation comprises: performing the erase operation on the plurality of memory cells included in the selected memory block among the plurality of memory blocks using a second duration time of the erase voltage shorter than the first duration time of the erase voltage when the second verify operation has failed. ### Claim 17 (depends on 14) The method according to claim 14, wherein the performing the second verify operation comprises: verifying threshold voltages of the plurality of memory cells included in the selected memory block to check whether the threshold voltages have reached a second verify voltage having a level higher than a level of the first verify voltage. ### Claim 18 (depends on 17) The method according to claim 17, wherein the performing the additional erase operation comprises: performing the erase operation on the plurality of memory cells included in the selected memory block among the plurality of memory blocks using a third duration time of the erase voltage shorter than the first duration time of the erase voltage when the second verify operation has passed. ### Claim 19 (depends on 17) The method according to claim 17, wherein the performing the additional erase operation comprises: performing the erase operation on the plurality of memory cells included in the selected memory block among the plurality of memory blocks using a fourth duration time of the erase voltage longer than the first duration time of the erase voltage when the second verify operation has failed.