# US 10,373,687 B2 · Semiconductor memory device and operation method thereof

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- Number: US 10,373,687 B2
- Document ID: US10373687B2
- Status: Granted
- Kind: B2
- Application number: 16/265,591
- Filed: 2019-02-01
- Published: 2019-05-30
- Granted: 2019-08-06
- Earliest claimed: 2017-08-11
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hee Youl Lee
- Web page: https://patentgrep.com/patent/US10373687B2

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/30: Power supply circuits
- G11C 16/32: Timing circuits
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes a plurality of memory cells coupled between a common source line and a bit line. The peripheral circuit controls a voltage supplied to the cell string to program a selected memory cell of the cell string by performing a program loop including a program section, a detrap section, and a verify section. Also, the peripheral circuit is configured to supply a program voltage to a word line coupled to the selected memory cell among the plurality of memory cells during the program section. The peripheral circuit further supplies a detrap voltage to the cell string during the detrap section and supplies a verify voltage to the word line during the verify section.

## Claims

### Claim 1

A semiconductor memory device comprising:
a cell string including a plurality of memory cells; and
a peripheral circuit configured to control a voltage supplied to the cell string to program a selected memory cell of the plurality of memory cells of the cell string,
wherein the peripheral circuit is further configured to apply a detrap voltage to the cell string after a program voltage is applied to a word line coupled to the selected memory cell in a program operation.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the detrap voltage is a voltage to increase a channel potential of the selected memory cell.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the cell string further comprises a source select transistor coupled between one of the plurality of memory cells and a common source line, and
wherein the detrap voltage is applied to the common source line.

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3, wherein the peripheral circuit is further configured to apply a first voltage smaller than the detrap voltage to a gate terminal of the source select transistor, while the detrap voltage is applied to the common source line.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein gate induced drain leakage (GIDL) current is generated at the source transistor due to the detrap voltage and the first voltage.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein the peripheral circuit is further configured to apply a second voltage smaller than the detrap voltage to the word line coupled to the selected memory cell, while the detrap voltage is applied to the common source line.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein the peripheral circuit is further configured to apply a detrap pass voltage to a word line coupled to a unselected memory cell among the plurality of memory cells, while the detrap voltage is applied to the common source line.

### Claim 8 (depends on 2)

The semiconductor memory device of claim 2, wherein the cell string further comprises a drain select transistor coupled between one of the plurality of memory cells and a bit line, and
wherein the detrap voltage is applied to the bit line.

### Claim 9 (depends on 8)

The semiconductor memory device of claim 8, wherein the peripheral circuit is further configured to apply a first voltage smaller than the detrap voltage to a gate terminal of the drain select transistor, while the detrap voltage is applied to the bit line.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9, wherein gate induced drain leakage (GIDL) current is generated at the drain transistor due to the detrap voltage and the first voltage.

### Claim 11 (depends on 10)

The semiconductor memory device of claim 10, wherein the peripheral circuit is further configured to apply a second voltage smaller than the detrap voltage to the word line coupled to the selected memory cell, while the detrap voltage is applied to the bit line.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein the peripheral circuit is further configured to apply a detrap pass voltage higher than the second voltage to a word line coupled to a unselected memory cell among the plurality of memory cells, while the detrap voltage is applied to the bit line.

### Claim 13 (depends on 2)

The semiconductor memory device of claim 2, wherein the detrap voltage is applied to a bulk region in which the cell string is formed.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, wherein the cell string further comprises a source select transistor coupled between one of the plurality of memory cells and a common source line, and
wherein the peripheral circuit is further configured to float the common source line, while the detrap voltage is applied to the bulk region.

### Claim 15 (depends on 14)

The semiconductor memory device of claim 14, wherein the peripheral circuit is further configured to apply a first voltage smaller than the detrap voltage to a gate terminal of the source select transistor, while the detrap voltage is applied to the bulk region.

### Claim 16 (depends on 15)

The semiconductor memory device of claim 15, wherein the gate induced drain leakage (GIDL) current is generated at the source transistor due to the detrap voltage and the first voltage.

### Claim 17 (depends on 16)

The semiconductor memory device of claim 16, wherein the peripheral circuit is further configured to apply a second voltage smaller than the detrap voltage to the word line coupled to the selected memory cell, while the detrap voltage is applied to the bulk region.

### Claim 18 (depends on 17)

The semiconductor memory device of claim 17, wherein the peripheral circuit is further configured to apply a detrap pass voltage higher than the second voltage to a word line coupled to a unselected memory cell among the plurality of memory cells, while the detrap voltage is applied to the bulk region.

### Claim 19

A method for operating a semiconductor memory device, the method comprising:
applying a program voltage to a word line coupled to a selected memory cell of a plurality of memory cells included in a cell string of the semiconductor memory device; and
performing a detrap operation, using a detrap voltage, on the selected memory cell.

### Claim 20 (depends on 19)

The method of claim 19, wherein performing the detrap operation comprises:
applying the detrap voltage to a common source line of the cell string; and
applying a first voltage smaller than the detrap voltage to a gate terminal of a source select transistor coupled to the common source line, to generate gate induced drain leakage (GIDL) current at the source select transistor.

### Claim 21 (depends on 19)

The method of claim 19, wherein performing the detrap operation comprises:
applying the detrap voltage to a bit line of the cell string; and
applying a first voltage smaller than the detrap voltage to a gate terminal of a drain select transistor coupled to the bit line, to generate gate induced drain leakage (GIDL) current at the drain select transistor.

### Claim 22 (depends on 19)

The method of claim 19, wherein performing the detrap operation comprises:
applying the detrap voltage to a bulk region in which the cell string is formed;
float a common source line coupled to the cell string; and
applying a first voltage smaller than the detrap voltage to a gate terminal of a source transistor coupled to the common source line, to generate gate induced drain leakage (GIDL) current at the source select transistor.

### Claim 23 (depends on 19)

The method of claim 19, wherein performing the detrap operation comprises:
applying a second voltage smaller than the detrap voltage to the word line coupled to the selected memory cell; and
applying a detrap pass voltage higher than the second voltage to a word line coupled to an unselected memory cell of the cell string.