# US 10,373,686 B2 · Three-dimensional flash NOR memory system with configurable pins

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,686 B2
- Document ID: US10373686B2
- Status: Granted
- Kind: B2
- Application number: 15/660,552
- Filed: 2017-07-26
- Published: 2017-11-09
- Granted: 2019-08-06
- Earliest claimed: 2013-12-02
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran; Hung Quoc Nguyen; Mark Reiten
- Web page: https://patentgrep.com/patent/US10373686B2

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 2207/105: Aspects related to pads, pins or terminals
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.

## Claims

### Claim 1

A three-dimensional memory system, comprising:
a plurality of pins coupled to a logic circuit, the logic circuit receiving a control signal; and
a memory array comprising a plurality of stacked dies, each die comprising memory cells;
an output stage comprising a sense amplifier, a plurality of buffers for receiving an output of the sense amplifier, and a plurality of pads for receiving an output of the plurality of buffers;
wherein the plurality of pins are configured by the logic circuit to perform a first function when the control signal has a first value and to perform a second function when the control signal has a second value, wherein the first function is providing addresses to the memory array for a read operation resulting in data being read by the sense amplifier, stored in the plurality of buffers, and output from the plurality of buffers onto the plurality of pads, and the second function is providing control signals for testing of the memory system.

### Claim 2 (depends on 1)

The system of claim 1, wherein the control signal is provided by a controller.

### Claim 3 (depends on 1)

The system of claim 1, wherein at least one of the plurality of pins is coupled to the logic circuit through a TSV.

### Claim 4 (depends on 1)

The system of claim 1, wherein at least one of the plurality of pins is a serial pin.

### Claim 5 (depends on 1)

The system of claim 1, wherein at least one of the plurality of pins is a parallel pin.