# US 10,373,685 B2 · Content addressable memory device having electrically floating body transistor

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- Number: US 10,373,685 B2
- Document ID: US10373685B2
- Status: Granted
- Kind: B2
- Application number: 16/013,646
- Filed: 2018-06-20
- Published: 2018-10-18
- Granted: 2019-08-06
- Earliest claimed: 2013-01-14
- Assignees: Zeno Semiconductor, Inc.
- Applicants: Zeno Semiconductor, Inc.
- Inventors: Benjamin S. Louie; Jin-Woo Han; Yuniarto Widjaja
- Web page: https://patentgrep.com/patent/US10373685B2

## CPC

- G11C 15/04: using semiconductor elements
- G11C 15/046: {using non-volatile storage elements}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 16/0458: {comprising two or more independent floating gates which store independent data}
- G11C 16/0475: {comprising two or more independent storage sites which store independent data}
- G11C 2211/4013: Memory devices with multiple cells per bit, e.g. twin-cells
- G11C 2211/4016: Memory devices with silicon-on-insulator cells
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

## Claims

### Claim 1

A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
a first floating body transistor;
a second floating body transistor; and
a third transistor;
wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node;
wherein said third transistor is electrically connected to said common node; and
wherein said first floating body transistor and said second floating body transistor store complementary data.

### Claim 2 (depends on 1)

The content addressable memory array of claim 1, wherein said first floating body transistor and said second floating body transistor comprise a buried well region.

### Claim 3 (depends on 1)

The content addressable memory array of claim 1, wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.

### Claim 4 (depends on 1)

The content addressable memory array of claim 1, wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region.

### Claim 5 (depends on 1)

The content addressable memory array of claim 1, wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.

### Claim 6 (depends on 1)

The content addressable memory array of claim 1, wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.

### Claim 7 (depends on 1)

The content addressable memory array of claim 1, wherein said third transistor comprises a third floating body transistor.

### Claim 8

A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
a first bi-stable floating body transistor; and
a second bi-stable floating body transistor;
wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor are electrically connected in series through a common node; and
wherein said first floating body transistor and said second floating body transistor store complementary data.

### Claim 9 (depends on 8)

The content addressable memory array of claim 8, wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor comprise a buried well region.

### Claim 10 (depends on 8)

The content addressable memory array of claim 8, wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor comprise a buried insulator region.

### Claim 11 (depends on 8)

The content addressable memory array of claim 8, wherein said first bi-stable floating body transistor comprises a first gate region and said second bi-stable floating body transistor comprises a second gate region.

### Claim 12 (depends on 8)

The content addressable memory array of claim 8, wherein each said content addressable memory cell further comprises an additional transistor.

### Claim 13 (depends on 12)

The content addressable memory array of claim 12, wherein said first bi-stable floating body comprises a first conductivity type and said additional transistor comprises said first conductivity type.

### Claim 14 (depends on 12)

The content addressable memory array of claim 12, wherein said first bi-stable floating body transistor comprises a first conductivity type and said additional transistor comprises a second conductivity type different from said first conductivity type.

### Claim 15 (depends on 8)

The content addressable memory array of claim 8, wherein each said content addressable memory cell further comprises a third bi-stable floating body transistor.

### Claim 16

A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
a first transistor having a first floating body;
a second transistor having a second floating body;
a third transistor;
a first drain region contacting said first floating body;
a second drain region contacting said second floating body;
a first source region contacting said first floating body, spaced apart from said first drain region; and
a second source region contacting said second floating body, spaced apart from said second drain region;
wherein said first and second drain regions are electrically connected to each other;
wherein said third transistor is electrically connected to said first and second drain regions; and
wherein said first floating body and said second floating body store complementary charge states.

### Claim 17 (depends on 16)

The content addressable memory array of claim 16, wherein said first transistor and said second transistor comprise a buried well region.

### Claim 18 (depends on 16)

The content addressable memory array of claim 16, wherein said first transistor and said second transistor comprise a buried insulator region.

### Claim 19 (depends on 16)

The content addressable memory array of claim 16, wherein said first transistor comprises a first gate region and said second transistor comprises a second gate region.

### Claim 20 (depends on 16)

The content addressable memory array of claim 16, wherein said first transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.

### Claim 21 (depends on 16)

The content addressable memory array of claim 16, wherein said first transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.

### Claim 22 (depends on 16)

The content addressable memory array of claim 16, further comprising a fourth transistor, having a third floating body.