# US 10,373,676 B2 · Semiconductor device, display panel, and electronic device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,676 B2
- Document ID: US10373676B2
- Status: Granted
- Kind: B2
- Application number: 15/383,100
- Filed: 2016-12-19
- Published: 2018-06-21
- Granted: 2019-08-06
- Earliest claimed: 2015-12-22
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Kei Takahashi; Takayuki Ikeda; Naoaki Tsutsui
- Web page: https://patentgrep.com/patent/US10373676B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G09G 3/36: using liquid crystals
- G09G 5/00: Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T)
- G11C 7/02: with means for avoiding parasitic signals
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- H10D 86/215: {comprising FinFETs}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Objects are to provide a semiconductor device with a novel structure, to provide a semiconductor device with high resistance to noise, to provide a semiconductor device with a small chip area, and to provide a semiconductor device with low power consumption. In a memory cell included in a frame memory, a transistor containing an oxide semiconductor and a transistor containing silicon are used in combination to retain charge, whereby data is retained. In this structure, turning off the transistor containing an oxide semiconductor can prevent data fluctuations even if power noise through a wiring is generated.

## Claims

### Claim 1

A semiconductor device comprising:
a frame memory comprising a memory cell comprising a first transistor, a second transistor, and a capacitor;
a source driver comprising a first buffer circuit comprising a first operational amplifier; and
a gate driver comprising a second buffer circuit comprising a second operational amplifier,
wherein the first operational amplifier is supplied with a first positive power supply voltage and a ground potential,
wherein the second operational amplifier is supplied with a second positive power supply voltage and a negative power supply voltage,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the capacitor,
wherein the first transistor in an off state is configured to make the gate of the second transistor retain charge corresponding to data, and
wherein a voltage applied to the gate of the first transistor to turn off the first transistor is lower than the ground potential, and is equal to the negative power supply voltage.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a voltage generator circuit,
wherein the voltage generator circuit is configured to generate the first positive power supply voltage, the ground potential, and the voltage applied to the gate of the first transistor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a channel formation region of the first transistor comprises an oxide semiconductor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a channel formation region of the second transistor comprises silicon.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein a layer comprising the first transistor is placed above a layer comprising the second transistor.

### Claim 6 (depends on 1)

A display panel comprising:
the semiconductor device according to claim 1; and
a display device.

### Claim 7 (depends on 6)

An electronic device comprising:
the display panel according to claim 6; and
a control unit.

### Claim 8

A semiconductor device comprising:
a frame memory comprising a memory cell comprising a first transistor, a second transistor, and a capacitor;
a source driver comprising a first buffer circuit comprising a first operational amplifier; and
a gate driver comprising a second buffer circuit comprising a second operational amplifier,
wherein the first operational amplifier is supplied with a first positive power supply voltage and a ground potential,
wherein the second operational amplifier is supplied with a second positive power supply voltage and a negative power supply voltage,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the capacitor,
wherein the first transistor in an off state is configured to make the gate of the second transistor retain charge corresponding to data,
wherein a first voltage applied to the gate of the first transistor to turn off the first transistor is lower than the ground potential,
wherein the negative power supply voltage is lower than the first voltage, and
wherein a second voltage applied to the gate of the first transistor to turn on the first transistor is lower than the first positive power supply voltage.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, further comprising a voltage generator circuit,
wherein the voltage generator circuit is configured to generate the first positive power supply voltage, the ground potential, the first voltage, and the second voltage.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, further comprising a display controller,
wherein the display controller is configured to transfer the data retained in the frame memory to the source driver in a period during which an output voltage of the first buffer circuit is stable in one gate scan period.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, wherein a channel formation region of the first transistor comprises an oxide semiconductor.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8, wherein a channel formation region of the second transistor comprises silicon.

### Claim 13 (depends on 8)

The semiconductor device according to claim 8, wherein a layer comprising the first transistor is placed above a layer comprising the second transistor.

### Claim 14 (depends on 8)

A display panel comprising:
the semiconductor device according to claim 8; and
a display device.

### Claim 15 (depends on 14)

An electronic device comprising:
the display panel according to claim 14; and
a control unit.