# US 10,373,674 B2 · Apparatuses and methods for data transmission offset values in burst transmissions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,674 B2 - Document ID: US10373674B2 - Status: Granted - Kind: B2 - Application number: 15/692,937 - Filed: 2017-08-31 - Published: 2019-02-28 - Granted: 2019-08-06 - Earliest claimed: 2017-08-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Wolfgang A. Spirkl - Web page: https://patentgrep.com/patent/US10373674B2 ## CPC - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 29/022: {in I/O circuitry} - G06F 13/16: for access to memory bus (G06F13/28 takes precedence) - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 29/028: {with adaption or trimming of parameters} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values. ## Claims ### Claim 1 An apparatus comprising: offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line, wherein the offset values are based on individual threshold voltage biases of sample circuits of the receiver circuit; and an input/output (I/O) circuit comprising a driver circuit, the driver circuit configured to receive a logic signal and the offset values, the driver circuit configured to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values, wherein the driver circuit comprises a driver configured to provide the output signal to the signal line based on pull-up and pull-down signals, wherein the pull-up and pull-down signals are based on the logic signal and the offset value, wherein the driver circuit further comprises an encoder coupled to the driver, wherein the encoder is configured to receive the logic signal and the offset values and to provide the pull-up and pull-down signals based on the logic signal and the offset values. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the encoder is configured to determine a voltage that corresponds to a first data slot of the logic signal and adjust the determined voltage based on an offset value of the offset values associated with the data slot to provide an output voltage, wherein the encoder is configured to provide the pull-up and pull-down signals based on the output voltage. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the encoder is configured to apply a first offset value of the offset values to a bit of the logic signal corresponding to a first data slot and to apply a second offset value of the offset values to a second bit of the logic signal corresponding to a second data slot. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the first offset value is different than the second offset value. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the first data slot is adjacent the second data slot. ### Claim 6 (depends on 3) The apparatus of claim 3, further comprising a training circuit configured to perform an interface training operation with the receiver circuit of the memory to determine the offset values. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the training circuit configured to perform the interface training operation comprises providing test signals with various voltage levels to the receiver circuit over the signal line and receiving signals back based on the test signals, wherein the offset values are determined based on the received signals. ### Claim 8 A method, comprising: receiving a logic signal; receiving offset values associated with a receiver circuit of a memory device coupled to a signal line, wherein the offset values are based on individual transition threshold voltage biases of sample circuits of the receiver circuit; determining a voltage to provide on the signal line based on the logic signal; applying the offset values to adjust the voltage to provide on the signal line by; applying a first offset value to the signal line for data slots corresponding to a first sample circuit of the receiver circuit; and applying a second offset value to the signal line for data slots corresponding to a second sample circuit of the receiver circuit; and providing the adjusted voltage on the signal line. ### Claim 9 (depends on 8) The method of claim 8, wherein the first offset value is different than the second offset value. ### Claim 10 (depends on 8) The method of claim 8, wherein the first data slot is a negative offset value and the second data slot is a positive offset value. ### Claim 11 (depends on 8) The method of claim 8, wherein applying the offset values to adjust the voltage to provide on the signal line comprises providing pull-up and pull-down signals for a driver. ### Claim 12 (depends on 8) The method of claim 8, further comprising performing an interface training operation with the receiver circuit of the memory to determine the offset values. ### Claim 13 (depends on 12) The method of claim 12, wherein performing the interface training operation comprises: providing test signals with various voltage levels to the receiver circuit over the signal line; receiving signals back based on the test signals; and determining the offset values based on the received signals.