# US 10,373,672 B2 · Command signal clock gating

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- Number: US 10,373,672 B2
- Document ID: US10373672B2
- Status: Granted
- Kind: B2
- Application number: 16/039,995
- Filed: 2018-07-19
- Published: 2019-02-28
- Granted: 2019-08-06
- Earliest claimed: 2017-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Parthasarathy Gajapathy
- Web page: https://patentgrep.com/patent/US10373672B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 7/109: {Control signal input circuits}
- G11C 7/1093: {Input synchronization}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 11/408: Address circuits
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

## Claims

### Claim 1

A semiconductor device, comprising:
a synchronous digital circuit configured to receive command address signals, wherein the synchronous digital circuit comprises a clock gating tree, comprising:
a first clock gating stage comprising a first flip-flop configured to be latched based on a clock signal; and
a second clock gating stage comprising a plurality of second flip-flops, wherein the plurality of second flip-flops are configured to be latched in response to an activate detection signal latched by the first flip-flop based on the clock signal,
wherein the semiconductor device comprises a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, comprising logic coupled to the first clock gating stage and configured to provide the activate detection signal to an input of the first flip-flop.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the logic provides the activate detection signal based on command address signals received from a device external to the semiconductor device.

### Claim 4

A semiconductor device, comprising:
a synchronous digital circuit configured to receive command address signals, wherein the synchronous digital circuit comprises a clock gating tree, comprising:
a first clock gating stage comprising a first flip-flop configured to be latched based on a clock signal; and
a second clock gating stage comprising a plurality of second flip-flops, wherein the plurality of second flip-flops are configured to be latched in response to an activate detection signal latched by the first flip-flop based on the clock signal, wherein each of the command address signals comprises a two-cycle command.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of second flip-flops are not clocked on every clock cycle of the clock signal.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein in response to the activate detection signal, the plurality of second flip-flops are configured to be clocked to latch the command address signals to one or more bank control blocks of one or more memory banks.