# US 10,373,671 B1 · Techniques for clock signal jitter generation

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- Number: US 10,373,671 B1
- Document ID: US10373671B1
- Status: Granted
- Kind: B1
- Application number: 15/948,422
- Filed: 2018-04-09
- Granted: 2019-08-06
- Earliest claimed: 2018-04-09
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Tyler J. Gomm
- Web page: https://patentgrep.com/patent/US10373671B1

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 7/588: {Random number generators, i.e. based on natural stochastic processes}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K 23/54: Ring counters, i.e. feedback shift register counters (H03K23/52 takes precedence)
- H03K 2005/00019: {Variable delay}
- H03L 7/08: Details of the phase-locked loop
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.

## Claims

### Claim 1

A device, comprising:
an integrated circuit; and
a jitter generator located on the integrated circuit, comprising:
a random number generator configured to generate a random number in response to a clock input signal;
delay-causing circuitry configured to receive the clock input signal, and wherein the delay-causing circuitry is configured to create a delayed clock input signal; and
a phase mixer configured to receive the random number, the delayed clock input signal, and the clock input signal, and wherein the phase mixer is configured to output a clock output signal comprising the clock input signal and jitter.

### Claim 2 (depends on 1)

The device of claim 1, wherein the jitter generator is configured to receive a first clocking signal or a second clocking signal as the clock input signal and is configured to output the clock output signal to a command decoder, a delay locked loop, or an input/output interface, or any combination thereof.

### Claim 3 (depends on 1)

The device of claim 1, wherein the delay-causing circuitry is configured to have a variable delay value, wherein the variable delay value is configured to vary based at least in part on an operational mode of the jitter generator.

### Claim 4 (depends on 3)

The device of claim 3, comprising a first variable capacitor and a second variable capacitor, wherein the first variable capacitor is configured to couple to the phase mixer, wherein the second variable capacitor is configured to couple to the delay-causing circuitry, and wherein the first variable capacitor and the second variable capacitor are configured to vary in a capacitance value based on the operational mode of the jitter generator.

### Claim 5 (depends on 3)

The device of claim 3, comprising a first variable capacitor and a second variable capacitor, wherein the first variable capacitor is configured to couple to the phase mixer, wherein the second variable capacitor is configured to couple to the delay-causing circuitry, and wherein the first variable capacitor and the second variable capacitor are configured to vary in a capacitance value based on a control signal configured to transmit from the random number generator.

### Claim 6 (depends on 5)

The device of claim 5, wherein the random number generator is configured to transmit one or more bits as the random number to the phase mixer, and wherein the control signal is configured to comprise a bit of the one or bits transmitted from the random number generator.

### Claim 7 (depends on 1)

The device of claim 1, comprising a first capacitor and a second capacitor, wherein the first capacitor is configured to couple to the phase mixer, and wherein the second capacitor is configured to couple to the delay-causing circuitry.

### Claim 8 (depends on 1)

The device of claim 1, wherein the delay-causing circuitry comprises combinational logic configured to delay the clock input signal an amount to create the delayed clock input signal.

### Claim 9 (depends on 1)

The device of claim 1, wherein the random number generator comprises a linear feedback shift register comprising a plurality of flip-flops and XOR gates, wherein the linear feedback shift register is configured to count in a pseudo-random counting order, and wherein the random number generator is configured to output the random number based at least in part on the pseudo-random counting order.

### Claim 10

A jitter generator, comprising:
a first variable capacitor configured to change a first value of capacitance in response to a first control signal, wherein the first variable capacitor is configured to receive a clock-in signal;
a second variable capacitor configured to change a second value of capacitance in response to the first control signal, wherein the second variable capacitor is configured to receive the clock-in signal;
a delay-causing circuitry configured to couple to the second variable capacitor, wherein the delay-causing circuitry is configured to receive the clock-in signal from the second variable capacitor, and wherein the delay-causing circuitry is configured to generate a delayed clock-in signal by delaying the clock-in signal;
a random number generator configured to receive the clock-in signal, and wherein the random number generator is configured to generate a random number in response to the clock-in signal; and
a phase mixer configured to receive the random number from the random number generator, to receive the clock-in signal from the first variable capacitor, and to receive the delayed clock-in signal from the delay-causing circuitry, and wherein the phase mixer is configured to generate a clock-out signal comprising the clock-in signal and added jitter.

### Claim 11 (depends on 10)

The jitter generator of claim 10, wherein the first variable capacitor and the second variable capacitor are each configured to have a third value of capacitance in response to a second control signal, and wherein the first variable capacitor and the second variable capacitor are each configured to have a fourth value of capacitance in response to a third control signal.

### Claim 12 (depends on 11)

The jitter generator of claim 11, wherein the delay-causing circuitry is configured to cause a variable amount of delay based at least in part on operational modes of the jitter generator, wherein a first operational mode corresponds to the first control signal, a second operational mode corresponds to the second control signal, and a third operational mode corresponds to the third control signal.

### Claim 13 (depends on 10)

The jitter generator of claim 10, wherein the random number generator comprises a linear feedback shift register having combinational logic configured to enable counting in a non-sequential order in response to the clock-in signal.

### Claim 14

A method, comprising:
receiving an input clock signal;
receiving a mode selection signal indicative of an operational mode;
delaying the input clock signal through transmission in delay-causing circuitry, wherein a delay of the input clock signal caused by the delay-causing circuitry changes a value of the delay in response to the mode selection signal; and
outputting, via a jitter generator, an output clock signal comprising the input clock signal and additional jitter, wherein the output clock signal is generated in response to a random number acting to mix phases of the input clock signal and a delayed input clock signal transmitted from the delay-causing circuitry.

### Claim 15 (depends on 14)

The method of claim 14, wherein one or more variable capacitors change capacitance value in response to the mode selection signal.

### Claim 16 (depends on 15)

The method of claim 15, wherein the delay-causing circuitry comprises one or more NAND logic gates and one or more inverting logical gates responsive to the mode selection signal.

### Claim 17

A method comprising:
receiving an input clock signal;
generating the random number by providing the input clock signal to pseudo-random counting circuitry, wherein the random number is represented with a plurality of bits;
transmitting a subset of the plurality of bits to one or more capacitors configured to activate in response to the subset of the plurality of bits, wherein a capacitance value of the one or more capacitors is configured to change in response to activation;
delaying the input clock signal through transmission in delay-causing circuitry; and
outputting an output clock signal comprising the input clock signal and additional jitter, wherein the output clock signal is generated in response to a random number acting to mix phases of the input clock signal and a delayed input clock signal transmitted from the delay-causing circuitry.

### Claim 18 (depends on 14)

The method of claim 14, comprising:
generating the random number by providing the input clock signal to a linear feedback shift register, wherein the linear feedback shift register is configured to count in a non-binary sequential order mimicking a pseudo-random counting order;
at a first rising edge of the input clock signal, providing the random number to a phase mixer through a parallel transmission of bits for a first binary number associated with the non-binary sequential order; and
at a second rising edge of the input clock signal, providing the random number to the phase mixer through the parallel transmission of bits for a second binary number associated with the non-binary sequential order.

### Claim 19 (depends on 14)

The method of claim 14, wherein the output clock signal comprises the additional jitter causing a Gaussian distribution of one or more amounts of jitter.

### Claim 20 (depends on 14)

The method of claim 14, wherein the input clock signal is an internal clock signal CLK, a phase controlled internal locked clock signal LCLK, or any combination thereof.