# US 10,373,668 B2 · Memory device shared by two or more processors and system including the same

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- Number: US 10,373,668 B2
- Document ID: US10373668B2
- Status: Granted
- Kind: B2
- Application number: 15/477,382
- Filed: 2017-04-03
- Published: 2017-11-23
- Granted: 2019-08-06
- Earliest claimed: 2016-05-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kwang Hyun Kim; Ki Seok Oh
- Web page: https://patentgrep.com/patent/US10373668B2

## CPC

- G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools}
- G06F 3/0673: {Single storage device}
- G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence)
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/40622: {Partial refresh of memory arrays}
- G06F 2212/1041: Resource optimization
- G06F 2212/657: Virtual address space management
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.

## Claims

### Claim 1

A common memory device shared by at least a first processor and a second processor, the common memory device comprising:
a memory cell array including a plurality of memory regions, the plurality of memory regions including at least a first memory region allocated for the first processor and a second memory region allocated for the second processor, the memory cell array electrically connected to a memory controller, and the memory controller electrically connected to the first processor via a first local bus and electrically connected to the second processor via a second local bus;
a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh operation is performed on at least one of the first and second memory regions; and
a refresh circuit configured to,
selectively perform the refresh operation on the first memory region and the second memory region based on the refresh masking information, and
store self-refresh masking information in response to receiving a mode register setting command.

### Claim 2 (depends on 1)

The common memory device of claim 1, wherein the refresh circuit is configured to not perform the refresh operation on the plurality of memory regions except for at least one of the first and second memory regions based on the refresh masking information.

### Claim 3 (depends on 1)

The common memory device of claim 1, wherein when the second processor is disabled or in a sleep mode, the refresh masking information indicates that second memory region is masked.

### Claim 4 (depends on 1)

The common memory device of claim 1, wherein the refresh masking information storage circuit is configured to further store size information of at least one of the first and second memory regions.

### Claim 5 (depends on 1)

The common memory device of claim 1, wherein a size of the first memory region is selected from among a plurality of predetermined sizes.

### Claim 6 (depends on 5)

The common memory device of claim 5, further comprising at least one pin configured to select the size of the first memory region from among the predetermined sizes.

### Claim 7 (depends on 5)

The common memory device of claim 5, wherein
a first logical address space associated with the first processor is mapped to a first physical address space associated with the first memory region; and
a second logical address space associated with the second processor is mapped to a second physical address space associated with the second memory region.

### Claim 8 (depends on 1)

The common memory device of claim 1, wherein
the memory cell array includes a plurality of memory banks;
at least one of the plurality of memory banks corresponds to the first memory region; and
the remaining memory banks of the plurality of memory banks corresponds to the second memory region.

### Claim 9 (depends on 1)

The common memory device of claim 1, wherein
the memory cell array includes a plurality of memory banks, and each of the plurality of memory banks includes a plurality of segments;
a desired segment in each of the plurality of memory banks corresponds to the first memory region; and
the remaining segments in each of the plurality of memory banks corresponds to the second memory region.

### Claim 10

A memory controller for a shared memory system, the memory controller configured to:
partition a memory device into a plurality of memory regions, each of the plurality of memory regions allocated to at least one of a first processor and a second processor, the first processor electrically connected to the memory controller via a first local bus, and the second processor electrically connected to the memory controller via a second local bus;
receive a command instruction from one of the first processor or the second processor;
determine a memory region of the plurality of memory regions associated with the received command instructions using a mapping table;
access the determined memory region in accordance with the received command instruction; and
transmit results of the access to the at least one of the first processor and the second processor issuing the received command instruction, wherein
the received command instruction is a refresh operation command; and
the controller is further configured to,
partition the memory device by setting a size of at least one of the memory regions based on an instruction received from one of the first processor or the second processor, and
cause the memory device to perform the refresh operation on the memory regions of the plurality of memory regions not indicated as being masked, based on masking information indicating a memory region of the plurality of memory regions to mask.

### Claim 11 (depends on 10)

The memory controller of claim 10, wherein the plurality of memory regions includes at least a first memory region associated with the first processor and a second memory region associated with the second processor.

### Claim 12 (depends on 10)

The memory controller of claim 10, wherein at least one of the memory regions of the plurality of memory regions is associated with both the first processor and the second processor.