# US 10,373,665 B2 · Parallel access techniques within memory sections through section independence > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,665 B2 - Document ID: US10373665B2 - Status: Granted - Kind: B2 - Application number: 15/066,573 - Filed: 2016-03-10 - Published: 2017-09-14 - Granted: 2019-08-06 - Earliest claimed: 2016-03-10 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Richard E. Fackenthal - Web page: https://patentgrep.com/patent/US10373665B2 ## CPC - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part} - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/221: {using ferroelectric capacitors} - G11C 11/2257: {Word-line or row circuits} - G11C 11/2293: {Timing circuits or methods} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell. ## Claims ### Claim 1 A method of operating a bank of ferroelectric memory cells having multiple sections of memory cells, comprising: activating a first memory cell; sensing a state of the first memory cell; identifying a second memory cell to be activated; determining that the second memory cell is independent of the first memory cell based at least in part on determining that sense components coupled with the second memory cell are different from sense components coupled with the first memory cell; latching, with a latch, a row line address associated with the first memory cell; precharging the first memory cell after latching the row line address; and activating the second memory cell after the first memory cell begins precharging, wherein the precharging comprises a portion of a write-back operation. ### Claim 2 (depends on 1) The method of claim 1, wherein the determining that the second memory cell is independent of the first memory cell comprises; determining a first section of memory cells that contains the first memory cell and a second section of memory cells that contains the second memory cell; and determining that the second section of memory cells is independent of the first section of memory cells based at least in part on determining that sense components coupled with the second section of memory cells are different from sense components coupled with the first section of memory cells. ### Claim 3 (depends on 1) The method of claim 1, wherein the memory cells are ferroelectric memory cells. ### Claim 4 (depends on 1) The method of claim 1, wherein identifying the second memory cell to be activated comprises: selecting a second address of the second memory cell based at least in part on a first address of the first memory cell to provide a location of the second memory cell that is in a different and non-adjacent section of memory cells than the first memory cell. ### Claim 5 (depends on 1) The method of claim 1, wherein activating the second memory cell while precharging the first memory cell comprises: identifying a delay time for activating the second memory cell in response to determining that the second memory cell is independent of the first memory cell, the delay time providing a first predetermined delay for activating the second memory cell when the second memory cell is independent of the first memory cell; and activating the second memory cell after the delay time. ### Claim 6 (depends on 1) The method of claim 1, further comprising: identifying a third memory cell to be activated; determining that the third memory cell is not independent of the second memory cell; precharging the second memory cell; and activating the third memory cell after precharging the second memory cell. ### Claim 7 (depends on 6) The method of claim 6, wherein activating the third memory cell after precharging the first memory cell comprises: identifying a second delay time for activating the third memory cell in response to determining that the third memory cell is in a non-adjacent section of memory cells as the second memory cell, the second delay time providing a second predetermined delay for activating the third memory cell after precharging the second memory cell; and activating the third memory cell after the second delay time. ### Claim 8 A method of operating a bank of ferroelectric memory cells having multiple sections of memory cells, comprising: activating a first memory cell; sensing a state of the first memory cell; identifying a second memory cell to be activated; determining that the second memory cell is independent of the first memory cell; identifying a delay time for activating the second memory cell in response to determining that the second memory cell is independent of the first memory cell, the delay time providing a first predetermined delay for activating the second memory cell when the second memory cell is independent of the first memory cell; precharging the first memory cell; and activating the second memory cell after the delay time and while precharging the first memory cell. ### Claim 9 (depends on 8) The method of claim 8, further comprising: identifying a third memory cell to be activated; determining that the third memory cell is not independent of the second memory cell; precharging the second memory cell; and activating the third memory cell after precharging the second memory cell. ### Claim 10 (depends on 9) The method of claim 9, wherein activating the third memory cell after precharging the first memory cell comprises: identifying a second delay time for activating the third memory cell in response to determining that the third memory cell is in a non-adjacent section of memory cells as the second memory cell, the second delay time providing a second predetermined delay for activating the third memory cell after precharging the second memory cell; and activating the third memory cell after the second delay time. ### Claim 11 (depends on 1) The method of claim 1, wherein different sections of multiple sections of memory cells include one or more of selection components or sense amplifier components that are independent of each other. ### Claim 12 (depends on 11) The method of claim 11, wherein the selection components comprise a latch circuit that latches a section address of a first section of memory cells containing the first memory cell during the precharging of the first memory cell. ### Claim 13 (depends on 8) The method of claim 8, wherein the determining that the second memory cell is independent of the first memory cell is based at least in part on: determining that a first section of memory cells contains the first memory cell and a second section of memory cells contains the second memory cell; and determining that the second section of memory cells is independent of the first section of memory cells. ### Claim 14 (depends on 8) The method of claim 8, wherein the memory cells are ferroelectric memory cells, and wherein the precharging is a portion of a write-back operation of the ferroelectric memory cells. ### Claim 15 (depends on 8) The method of claim 8, wherein different sections of multiple sections of memory cells include one or more of selection components or sense amplifier components that are independent of each other. ### Claim 16 (depends on 15) The method of claim 15, wherein the selection components comprise a latch circuit that latches a section address of a first section of memory cells containing the first memory cell during the precharging of the first memory cell. ### Claim 17 (depends on 8) The method of claim 8, wherein identifying the second memory cell to be activated comprises: selecting a second address of the second memory cell based at least in part on a first address of the first memory cell to provide a location of the second memory cell that is in a different and non-adjacent section of memory cells than the first memory cell.