# US 10,373,661 B2 · Stacked semiconductor device and system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,661 B2 - Document ID: US10373661B2 - Status: Granted - Kind: B2 - Application number: 15/479,971 - Filed: 2017-04-05 - Published: 2017-12-07 - Granted: 2019-08-06 - Earliest claimed: 2016-06-01 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hae-Suk Lee; Reum Oh; Jin-Seong Park; Seung-Han Woo - Web page: https://patentgrep.com/patent/US10373661B2 ## CPC - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)} - H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H10W 90/00: Package configurations - H03K 3/356156: {with synchronous operation} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A stacked semiconductor device includes a plurality of semiconductor dies stacked in a vertical direction, first and second signal paths, a transmission unit and a reception unit. The first and second signal paths electrically connect the plurality of semiconductor dies, where each of the first signal path and the second signal path includes at least one through-substrate via. The transmission unit generates a first driving signal and a second driving signal in synchronization with transitioning timing of a transmission signal to output the first driving signal to the first signal path and output the second driving signal to the second signal path. The reception unit receives a first attenuated signal corresponding to the first driving signal from the first signal path and receives a second attenuated signal corresponding to the second driving signal from the second signal path to generate a reception signal corresponding to the transmission signal. ## Claims ### Claim 1 A stacked semiconductor device comprising: a plurality of semiconductor dies stacked in a vertical direction; a first signal path and a second signal path each electrically connecting the plurality of semiconductor dies, the first signal path and the second signal path each including at least one through-substrate via (TSV); a transmitter configured to generate a first driving signal and a second driving signal based on a transmission signal, the transmission signal including at least one first pulse having a pulse width such that, when the first driving signal and the second driving signal are attenuated through the first signal path to generate a first attenuated signal and the second signal path to generate a second attenuated signal, respectively, each of the first attenuated signal and the second attenuated signal have a rising time and a falling time longer than the pulse width of the first pulse included in the transmission signal received by the transmitter while the first attenuated signal and the second attenuated signal swing between a first supply voltage and a second supply voltage, and to output the first driving signal and the second driving signal to the first signal path and the second signal path, respectively; and a receiver configured to, receive the first attenuated signal via the first signal path and receive the second attenuated signal via the second signal path, the first attenuated signal being based on the first driving signal and the second attenuated signal being based on the second driving signal, and generate a reception signal based on the transmission signal such that the reception signal includes a second pulse with the pulse width thereof equal to the pulse width of the first pulse and less than the rising time and the falling time of each of the first attenuated signal and the second attenuated signal. ### Claim 2 (depends on 1) The stacked semiconductor device of claim 1, wherein the transmitter is configured to generate the first driving signal and the second driving signal such that the first driving signal toggles in synchronization with rising edges of the transmission signal and the second driving signal toggles in synchronization with falling edges of the transmission signal. ### Claim 3 (depends on 1) The stacked semiconductor device of claim 1, wherein the transmission signal and the reception signal are clock signals or data strobe signals, and the reception signal is a delayed version of the transmission signal such that a duty ratio of the reception signal is same as a duty ratio of the transmission signal. ### Claim 4 (depends on 3) The stacked semiconductor device of claim 3, wherein the transmitter is configured to generate the first driving signal and the second driving signal based on the transmission signal such that a frequency of the first driving signal, the second driving signal, the first attenuated signal and the second attenuated signal is half of a frequency of the transmission signal and the reception signal. ### Claim 5 (depends on 1) The stacked semiconductor device of claim 1, wherein the transmitter comprises: an encoder configured to generate a first encoder signal and a second encoder signal in synchronization with a timing of a transition of the transmission signal; a first driver configured to generate the first driving signal based on the first encoder signal; and a second driver configured to generate the second driving signal based on the second encoder signal. ### Claim 6 (depends on 5) The stacked semiconductor device of claim 5, wherein the encoder comprises: a first flip-flop having a clock terminal, a data terminal, an inversion output terminal and a non-inversion output terminal, the clock terminal configured to receive the transmission signal, the data terminal connected to the inversion output terminal, and the non-inversion output terminal configured to output the first encoder signal; and a second flip-flop having a clock terminal, a data terminal, an inversion output terminal, and a non-inversion output terminal, the clock terminal configured to receive an inverted version of the transmission signal, the data terminal connected to the inversion output terminal, and the non-inversion output terminal configured to output the second encoder signal. ### Claim 7 (depends on 1) The stacked semiconductor device of claim 1, wherein the receiver comprises: a first reception buffer configured to buffer the first attenuated signal to generate a first buffer signal; a second reception buffer configured to buffer the second attenuated signal to generate a second buffer signal; and a decoder configured to generate the reception signal based on the first buffer signal and the second buffer signal. ### Claim 8 (depends on 7) The stacked semiconductor device of claim 7, wherein the decoder comprises: a logic gate configured to perform an exclusive OR (XOR) operation on the first buffer signal and the second buffer signal to generate the reception signal. ### Claim 9 (depends on 1) The stacked semiconductor device of claim 1, wherein the transmitter comprises: an encoder configured to generate the first driving signal and the second driving signal such that the first driving signal and the second driving signal toggle in synchronization with rising edges and falling edges of the transmission signal, respectively. ### Claim 10 (depends on 9) The stacked semiconductor device of claim 9, wherein the receiver comprises: a decoder configured to perform an XOR operation on the first attenuated signal and the second attenuated signal to generate the reception signal. ### Claim 11 (depends on 1) The stacked semiconductor device of claim 1, wherein the transmitter is included in a first semiconductor die of the plurality of semiconductor dies, and the receiver is included in a second semiconductor die of the plurality of semiconductor dies. ### Claim 12 (depends on 1) The stacked semiconductor device of claim 1, further comprising: a third signal path and a fourth signal path electrically connecting the plurality of semiconductor dies, each of the third signal path and the fourth signal path including at least one TSV; and at least one internal circuit configured to generate a repair control signal, if at least one of the first signal path and the second signal path is defective, the repair control signal instructing the stacked semiconductor device to replace the first signal path and the second signal path with the third signal path and the fourth signal path, respectively. ### Claim 13 A system comprising: a base substrate; a plurality of semiconductor dies stacked on the base substrate in a vertical direction; a first signal path and a second signal path electrically connecting the plurality of semiconductor dies, each of the first signal path and the second signal path including at least one through-substrate via (TSV); a transmitter configured to generate a first driving signal and a second driving signal based on a transmission signal, the transmission signal including at least one first pulse having a pulse width such that, when the first driving signal and the second driving signal are attenuated through the first signal path to generate a first attenuated signal and the second signal path to generate a second attenuated signal, respectively, each of the first attenuated signal and the second attenuated signal have a rising time and a falling time longer than the pulse width of the first pulse included in the transmission signal received by the transmitter while the first attenuated signal and the second attenuated signal swing between a first supply voltage and a second supply voltage, and to output the first driving signal and the second driving signal to the first signal path and the second signal path, respectively; and a receiver configured to, receive the first attenuated signal via the first signal path and receive the second attenuated signal via the second signal path, the first attenuated signal being based on the first driving signal and the second attenuated signal being based on the second driving signal, and generate a reception signal corresponding to the transmission signal such that the reception signal includes a second pulse with the pulse width thereof equal to the pulse width of the first pulse and less than the rising time and the falling time of each of the first attenuated signal and the second attenuated signal. ### Claim 14 (depends on 13) The system of claim 13, wherein the transmitter is configured to generate the first driving signal and the second driving signal such that the first driving signal toggles in synchronization with rising edges of the transmission signal and the second driving signal toggles in synchronization with falling edges of the transmission signal. ### Claim 15 A stacked semiconductor device comprising: a first semiconductor die including a first transceiver, the first transceiver configured to transmit a first driving signal and a second driving signal to a first through-substrate via (TSV) and a second TSV, respectively, the first driving signal and the second driving signal being based on a transmission signal, the transmission signal including at least one first pulse having a pulse width such that, when the first driving signal and the second driving signal are attenuated through the first TSV and the second TSV to generate attenuated versions thereof, the attenuated versions of the first driving signal and the second driving signal have rising and falling times longer than the pulse width of the first pulse included in the transmission signal received by the first transceiver while the attenuated versions of the first driving signal and the second driving signal swing between a first supply voltage and a second supply voltage; and a second semiconductor die connected to the first semiconductor die via the first TSV and the second TSV, the second semiconductor die including a second transceiver, the second transceiver configured to, receive the attenuated versions of the first driving signal and the second driving signal via the first TSV and the second TSV, respectively, and to generate a reception signal based on the attenuated versions of the first driving signal and the second driving signal such that a duty cycle of the reception signal generated by the second transceiver is same as a duty cycle of the transmission signal received by the first transceiver such that the reception signal includes a second pulse with the pulse width thereof equal to the pulse width of the first pulse and less than the rising and falling times of the attenuated versions of the first driving signal and the second driving signal. ### Claim 16 (depends on 15) The stacked semiconductor device of claim 15, wherein the first transceiver is further configured to generate the first driving signal and the second driving signal such that the first driving signal and the second driving signal toggle in synchronization with rising edges and falling edges of the transmission signal, respectively, and a frequency of each of the first driving signal and the second driving signal is half of a frequency of the transmission signal. ### Claim 17 (depends on 15) The stacked semiconductor device of claim 15, wherein the first transceiver includes at least a transmitter, the transmitter including, an encoder configured to generate a first encoder signal and a second encoder signal in synchronization with a timing of a transition of the transmission signal, one or more drivers configured to generate the first driving signal and the second driving signal based on the first encoder signal and the second encoder signal, respectively; and the second transceiver includes at least a receiver, the receiver including, one or more reception buffers configured to buffer the attenuated versions of the first driving signal and the second driving signal to generate a first buffer signal and a second buffer signal, respectively, and a decoder configured to generate the reception signal based on the first buffer signal and the second buffer signal. ### Claim 18 (depends on 15) The stacked semiconductor device of claim 15, wherein the stacked semiconductor device is configured to transmit the transmission signal between first semiconductor die and the second semiconductor die while maintaining a same pulse width and a duty ratio between the transmission signal and the reception signal irrespective of a size of the pulse width of the transmission signal and a frequency of the transmission signal.