# US 10,373,660 B1 · Apparatuses and methods for duty cycle distortion correction of clocks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,660 B1 - Document ID: US10373660B1 - Status: Granted - Kind: B1 - Application number: 16/274,992 - Filed: 2019-02-13 - Published: 2019-08-29 - Granted: 2019-08-06 - Earliest claimed: 2018-02-23 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Hyun Yoo Lee; Kang-Yong Kim; John D. Porter - Web page: https://patentgrep.com/patent/US10373660B1 ## CPC - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 7/225: {Clock input buffers} - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - H03K 5/1565: {the output pulses having a constant duty cycle} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode. ## Claims ### Claim 1 An apparatus, comprising: a gain circuit comprising a first variable resistance coupled from a first output node to a reference voltage node and a second variable resistance coupled from a second output node to the reference voltage node, each of the first and second variable resistances is configured to have a first resistance in a first mode and a second resistance in a second mode, wherein the gain circuit is configured to provide output complementary clocks at the first output node and the second output nodes, respectively, and to cause a first voltage difference between the output complementary clocks in the first mode to be lower than a second voltage difference between the output complementary clocks in the second mode. ### Claim 2 (depends on 1) The apparatus of claim 1 further comprising a first input transistor and a second input transistor coupled between a current source and the first and second output nodes, respectively, wherein the first and second input transistors are configured to provide current from the current source to the first and second variable resistances responsive to input complementary clocks. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the gain circuit is configured to provide current from the current source to the first and second input transistors responsive to an enable signal provided by a command decoder. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first and second variable resistances are coupled to a common signal line and are configured to change resistance values responsive to a duty cycle correction signal at the common signal line. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein: the first variable resistance includes a first transistor and a first resistor coupled in series between the first output node and the reference voltage node; and the second variable resistance includes a second transistor and a second resistor coupled in series between the second output node and the reference voltage node; wherein each of the first and second transistors is coupled to the common signal line to change the resistance values of the first and second variable resistances, respectively, responsive to the duty cycle correction signal at the common signal line. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein: the first variable resistance includes a third resistor coupled between the first output node and the reference voltage node, and also coupled in parallel with the series coupled first transistor and first resistor; and the second variable resistance includes a fourth resistor coupled between the second output node and the reference voltage node, and also coupled in parallel with the series coupled second transistor and second resistor. ### Claim 7 (depends on 4) The apparatus of claim 4 further comprising a resistance circuit coupled between the first and second output nodes to cause a first crossing point of the output complementary clocks in the first mode to be lower than a second crossing point of the output complementary clocks in the second mode. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the resistance circuit comprises a resistor and at least a transistor coupled to the common signal line to provide a resistance between the first and second output nodes when the duty cycle correction signal is active. ### Claim 9 An apparatus, comprising: a first gain circuit comprising a first variable resistance coupled from a first output node to a first reference voltage node and a second variable resistance coupled from a second output node to the first reference voltage node; and a second gain circuit coupled to the first gain circuit and configured provide first output complementary clocks, and to cause a first voltage difference between the first output complementary clocks in a first mode to be lower than a second voltage difference between the first output complementary clocks in a second mode. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the second gain circuit comprises a third variable resistance coupled from a third output node to a second reference voltage node and a fourth variable resistance coupled from a fourth output node to the second reference voltage node, and wherein the second gain circuit is configured to provide the first output complementary clocks at the fourth output node and the third output nodes, respectively. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the first gain circuit is further configured to receive current from a first current source responsive to input complementary clocks and provide second output complementary clocks at the first output node and the second output node, respectively. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the second gain circuit is further configured to receive current from a second current source responsive to the second output complementary clocks from the first gain circuit. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the first gain circuit comprises a first input transistor and a second input transistor coupled between a current source and the first and second output nodes, respectively, wherein the first and second input transistors are configured to provide the current from the first current source to the first and second variable resistances responsive to the input complementary clocks. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the first gain circuit is configured to provide the current from the first current source to the first and second input transistors responsive to an enable signal provided by a command decoder. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the second gain circuit further comprises a third input transistor and a fourth input transistor coupled between the second current source and the third and fourth output nodes, respectively, wherein the third and fourth input transistors are configured to provide the current from the second current source to the third and fourth variable resistances, respectively, responsive to the second output complementary signals at the third and fourth output nodes. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein: the first and second variable resistances are coupled to a common signal line and are configured to change resistance values responsive to a duty cycle correction signal at the common signal line; and the third and fourth variable resistances are coupled to the common signal line and are configured to change resistance values responsive to the duty cycle correction signal at the common signal line. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein: the first variable resistance includes a first transistor and a first resistor coupled in series between the first output node and the first reference voltage node; and the second variable resistance includes a second transistor and a second resistor coupled in series between the second output node and the first reference voltage node; the third variable resistance includes a third transistor and a third resistor coupled in series between the third output node and the second reference voltage node; and the fourth variable resistance includes a fourth transistor and a fourth resistor coupled in series between the fourth output node and the second reference voltage node; wherein each of the first, second, third and fourth transistors is coupled to the common signal line to change the resistance values of the first, the second, the third and the fourth variable resistances, respectively, responsive to the duty cycle correction signal at the common signal line. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein: the first variable resistance includes a fifth resistor coupled between the first output node and the first reference voltage node, and also coupled in parallel with the series coupled first transistor and the first resistor; the second variable resistance includes a sixth resistor coupled between the second output node and the first reference voltage node, and also coupled in parallel with the series coupled second transistor and the second resistor; the third variable resistance includes a seven resistor coupled between the first output node and the second reference voltage node, and also coupled in parallel with the series coupled third transistor and the third resistor; and the fourth variable resistance includes an eighth resistor coupled between the second output node and the second reference voltage node, and also coupled in parallel with the series coupled fourth transistor and the fourth resistor. ### Claim 19 (depends on 16) The apparatus of claim 16 further comprising a resistance circuit coupled between the first and second output nodes to cause a first crossing point of the output complementary clocks in the first mode to be lower than a second crossing point of the output complementary clocks in the second mode. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the resistance circuit comprise a resistor and at least a transistor coupled to the common signal line to provide a resistance between the first and second output nodes when the duty cycle correction signal is active.