# US 10,373,658 B2 · Semiconductor modules > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,658 B2 - Document ID: US10373658B2 - Status: Granted - Kind: B2 - Application number: 15/638,906 - Filed: 2017-06-30 - Published: 2019-01-03 - Granted: 2019-08-06 - Earliest claimed: 2017-06-30 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sang Jin Byeon - Web page: https://patentgrep.com/patent/US10373658B2 ## CPC - G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 7/1066: {Output synchronization} - G11C 7/1069: {I/O lines read out arrangements} - G11C 8/04: using a sequential addressing device, e.g. shift register, counter - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - H05K 1/14: Structural association of two or more printed circuits (providing electric connection to or between printed circuits H05K1/11, H01R12/00) - H10F 77/50: Encapsulations or containers (for photovoltaic modules H10F19/80) - G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines - G11C: STATIC STORES (semiconductor memory devices H10B) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode. ## Claims ### Claim 1 A semiconductor module comprising: a host configured to include a first host line and a second host line; a first semiconductor device configured to include a first channel and a second channel; and a second semiconductor device configured to include a third channel and a fourth channel, wherein the first host line is connected to the first and third channels or to the first and second channels according to a set mode, and wherein the second host line is connected to the second and fourth channels or to the third and fourth channels according to the set mode. ### Claim 2 (depends on 1) The semiconductor module of claim 1, wherein if the set mode is a first set mode, the first host line is connected to the first and third channels to receive or output a first signal and the second host line is connected to the second and fourth channels to receive or output a second signal. ### Claim 3 (depends on 1) The semiconductor module of claim 1, wherein if the set mode is a second set mode, the first host line is connected to the first and second channels to receive or output a first signal and the second host line is connected to the third and fourth channels to receive or output a second signal. ### Claim 4 (depends on 1) The semiconductor module of claim 1, wherein if the set mode is a third set mode, the first host line is connected to the first and second channels to receive or output a first signal and the second host line is connected to the third and fourth channels to receive or output a second signal after the first host line is connected to the first channel to receive or output the first signal and the second host line is connected to the second channel to receive or output the second signal. ### Claim 5 (depends on 4) The semiconductor module of claim 4, wherein the third set mode is set to correspond to a case that an operation speed of the first semiconductor device is faster than an operation speed of the second semiconductor device. ### Claim 6 (depends on 1) The semiconductor module of claim 1, wherein the first semiconductor device includes: a first memory circuit configured to receive or output a signal through a first input and output (I/O) line; a second memory circuit configured to receive or output a signal through a second input and output (I/O) line; the first channel configured to connect the first host line to at least one of a first transmission line and the first input and output (I/O) line to receive or output a first signal, according to the set mode; and the second channel configured to connect the second host line to at least one of a second transmission line and the second input and output (I/O) line to receive or output a second signal, according to the set mode, wherein the first and second input and output (I/O) lines are connected to each other through a first internal transmission line according to the set mode. ### Claim 7 (depends on 6) The semiconductor module of claim 6, wherein the first channel includes: a first switch control circuit configured to generate first to fourth switch control signals according to a first command and a first module information signal; and a first selection and transmission (selection/transmission) circuit configured to control connection between the first host line, the first transmission line and the first input and output (I/O) line as well as connection between the first input and output (I/O) line and the first internal transmission line, in response to the first to fourth switch control signals. ### Claim 8 (depends on 6) The semiconductor module of claim 6, wherein the second channel includes: a second switch control circuit configured to generate fifth to eighth switch control signals according to a first command and a first module information signal; and a second selection/transmission circuit configured to control connection between the second host line, the second transmission line and the second input and output (I/O) line as well as connection between the second input and output (I/O) line and the first internal transmission line, in response to the fifth to eighth switch control signals. ### Claim 9 (depends on 1) The semiconductor module of claim 1, wherein the second semiconductor device includes: a third memory circuit configured to receive or output a signal through a third input and output (I/O) line; a fourth memory circuit configured to receive or output a signal through a fourth input and output (I/O) line; the third channel configured to connect a first transmission line to at least one of a third transmission line and the third input and output (I/O) line to receive or output a first signal, according to the set mode; and the fourth channel configured to connect a second transmission line to at least one of a fourth transmission line and the fourth input and output (I/O) line to receive or output a second signal, according to the set mode, wherein the third and fourth input and output (I/O) lines are connected to each other through a second internal transmission line according to the set mode. ### Claim 10 (depends on 9) The semiconductor module of claim 9, wherein the third channel includes: a third switch control circuit configured to generate ninth to twelfth switch control signals according to a second command and a second module information signal; and a third selection/transmission circuit configured to control connection between the first transmission line, a third transmission line and the third input and output (I/O) line as well as connection between the third input and output (I/O) line and the second internal transmission line, in response to the ninth to twelfth switch control signals. ### Claim 11 (depends on 6) The semiconductor module of claim 6, wherein the fourth channel includes: a fourth switch control circuit configured to generate thirteenth to sixteenth switch control signals according to a second command and a second module information signal; and a fourth selection/transmission circuit configured to control connection between the second transmission line, a fourth transmission line and the fourth input and output (I/O) line as well as connection between the fourth input and output (I/O) line and the second internal transmission line, in response to the thirteenth to sixteenth switch control signals. ### Claim 12 A semiconductor module comprising: a host configured to include a first host line and a second host line; a first semiconductor device configured to include a plurality of channels; and a second semiconductor device configured to include a plurality of channels, wherein if a set mode is a first set mode, the first and second host lines are connected to the plurality of channels included in one semiconductor device having a faster operation speed out of the first and second semiconductor devices to receive or output a signal, and thereafter one of the first and second host lines is connected to the plurality of channels included in the other semiconductor device having a slower operation speed out of the first and second semiconductor devices to receive or output a signal. ### Claim 13 (depends on 12) The semiconductor module of claim 12, wherein if the set mode is a second set mode, the first host line is connected to one of the plurality of channels included in the first semiconductor device and one of the plurality of channels included in the second semiconductor device to receive or output a first signal and the second host line is connected to another one of the plurality of channels included in the first semiconductor device and another one of the plurality of channels included in the second semiconductor device to receive or output a second signal. ### Claim 14 (depends on 12) The semiconductor module of claim 12, wherein if the set mode is a third set mode, the first host line is connected to the plurality of channels included in the first semiconductor device to receive or output a first signal and the second host line is connected to the plurality of channels included in the second semiconductor device to receive or output a second signal. ### Claim 15 (depends on 12) The semiconductor module of claim 12, wherein the first semiconductor device includes: a first memory circuit configured to receive or output a signal through a first input and output (I/O) line; a second memory circuit configured to receive or output a signal through a second input and output (I/O) line; a first channel configured to connect the first host line to at least one of a first transmission line and the first input and output (I/O) line to receive or output a first signal, according to the set mode; and a second channel configured to connect the second host line to at least one of a second transmission line and the second input and output (I/O) line to receive or output a second signal, according to the set mode, wherein the first and second input and output (I/O) lines are connected to each other through a first internal transmission line according to the set mode. ### Claim 16 (depends on 15) The semiconductor module of claim 15, wherein the first channel includes: a first switch control circuit configured to generate first to fourth switch control signals according to a first command and a first module information signal; and a first selection and transmission (selection/transmission) circuit configured to control connection between the first host line, the first transmission line and the first input and output (I/O) line as well as connection between the first input and output (I/O) line and the first internal transmission line, in response to the first to fourth switch control signals. ### Claim 17 (depends on 15) The semiconductor module of claim 15, wherein the second channel includes: a second switch control circuit configured to generate fifth to eighth switch control signals according to a first command and a first module information signal; and a second selection/transmission circuit configured to control connection between the second host line, the second transmission line and the second input and output (I/O) line as well as connection between the second input and output (I/O) line and the first internal transmission line, in response to the fifth to eighth switch control signals. ### Claim 18 (depends on 12) The semiconductor module of claim 12, wherein the second semiconductor device includes: a third memory circuit configured to receive or output a signal through a third input and output (I/O) line; a fourth memory circuit configured to receive or output a signal through a fourth input and output (I/O) line; a third channel configured to connect a first transmission line to at least one of a third transmission line and the third input and output (I/O) line to receive or output a first signal, according to the set mode; and a fourth channel configured to connect a second transmission line to at least one of a fourth transmission line and the fourth input and output (I/O) line to receive or output a second signal, according to the set mode, wherein the third and fourth input and output (I/O) lines are connected to each other through a second internal transmission line according to the set mode. ### Claim 19 (depends on 18) The semiconductor module of claim 18, wherein the third channel includes: a third switch control circuit configured to generate ninth to twelfth switch control signals according to a second command and a second module information signal; and a third selection/transmission circuit configured to control connection between the first transmission line, a third transmission line and the third input and output (I/O) line as well as connection between the third input and output (I/O) line and the second internal transmission line, in response to the ninth to twelfth switch control signals. ### Claim 20 (depends on 18) The semiconductor module of claim 18, wherein the fourth channel includes: a fourth switch control circuit configured to generate thirteenth to sixteenth switch control signals according to a second command and a second module information signal; and a fourth selection/transmission circuit configured to control connection between the second transmission line, a fourth transmission line and the fourth input and output (I/O) line as well as connection between the fourth input and output (I/O) line and the second internal transmission line, in response to the thirteenth to sixteenth switch control signals.