# US 10,373,656 B2 · Memory system that carries out temperature-based access to a memory chip

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,656 B2
- Document ID: US10373656B2
- Status: Granted
- Kind: B2
- Application number: 15/694,601
- Filed: 2017-09-01
- Published: 2018-03-29
- Granted: 2019-08-06
- Earliest claimed: 2016-09-26
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Marie Takada; Masanobu Shirakawa
- Web page: https://patentgrep.com/patent/US10373656B2

## CPC

- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory system is connectable to a host and comprises a memory chip including a nonvolatile semiconductor memory cell array, a memory controller, a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller, and a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip. The memory controller is configured to compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature and carry out access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.

## Claims

### Claim 1

A memory system connectable to a host, comprising:
a memory chip including a nonvolatile semiconductor memory cell array;
a memory controller including an error correcting code (ECC) circuit;
a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller; and
a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip, wherein
the memory controller is configured to, prior to performing a read access to the memory chip:
compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature,
carry out the read access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature, and
block the read access to the memory chip and operate the ECC circuit using dummy data, when neither the first temperature is greater than the first threshold temperature nor the second temperature is greater than the second threshold temperature.

### Claim 2 (depends on 1)

The memory system according to claim 1, wherein
the ECC circuit includes an encoding circuit, and the memory controller causes the encoding circuit to encode the dummy data.

### Claim 3 (depends on 1)

The memory system according to claim 1, wherein
the ECC circuit includes a decoding circuit, and the memory controller causes the decoding circuit to decode the dummy data.

### Claim 4 (depends on 1)

The memory system according to claim 1, wherein
the read access is included in an operation of copying data from a block of the nonvolatile semiconductor memory cell array to another block of the semiconductor memory cell array.

### Claim 5 (depends on 1)

The memory system according to claim 1, wherein
the memory controller is configured to carry out an initial read access of the memory chip without regard to the first and second temperatures in response to a read command received from the host, and then compares the first temperature against the first threshold temperature and the second temperature against the second threshold temperature when the initial read access fails.

### Claim 6

A memory system connectable to a host, comprising:
a plurality of memory chips, each of which includes a nonvolatile semiconductor memory cell array;
a memory controller;
a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller; and
a plurality of second temperature sensors, each of which is positioned to measure a second temperature representative of a temperature of one of the memory chips, wherein
the memory controller is configured to, prior to performing a read access to the memory chips, compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature, and perform a heating operation while preventing the read access to the memory chips when neither the first temperature is greater than the first threshold temperature nor at least one of the second temperatures is greater than the second threshold temperature.

### Claim 7 (depends on 6)

The memory system according to claim 6, wherein
the memory controller includes an error correcting code (ECC) circuit, and operates the ECC circuit to perform the heating operation.

### Claim 8 (depends on 6)

The memory system according to claim 6, wherein
the memory controller is configured to select one of the memory chips having a temperature higher than the second threshold temperature, as a target memory chip to be accessed.

### Claim 9 (depends on 6)

The memory system according to claim 6, wherein
the memory controller is configured to determine a target memory chip to be accessed based on a write command received from the host, and change the target memory chip if the temperature corresponding to the target memory chip is lower than the second threshold temperature and if one of the other memory chips has a temperature that is higher than the second threshold temperature.

### Claim 10

A method for operating a memory system including a memory chip having a nonvolatile semiconductor memory cell array, and a memory controller, the method comprising:
detecting a first temperature of the memory controller;
detecting a second temperature of the memory chip;
comparing the first temperature of the memory controller against a first threshold temperature;
comparing the second temperature of the memory chip against a second threshold temperature;
accessing the memory chip to carry out an operation in response to a read command from a host, when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature; and
performing a heating operation in response to the read command from the host while preventing a read access to the memory chip, when neither the first temperature is greater than the first threshold temperature nor the second temperature is greater than the second threshold temperature.

### Claim 11 (depends on 10)

The method according to claim 10, wherein
the memory controller includes an error correcting code (ECC) circuit, and
the heating operation includes operating the ECC circuit.

### Claim 12 (depends on 10)

The method according to claim 10, further comprising:
accessing the memory chip without regard to the first and second temperatures in response to an earlier command received from the host prior to the read command; and
only after detecting that access to the memory chip in response to the earlier command failed, performing the conditional read access to the memory chip based on the detected first and second temperatures, and the first and second threshold temperatures.

### Claim 13 (depends on 3)

The memory system according to claim 3, wherein
after the decoding circuit has decoded the dummy data, the memory controller reads data from the memory chip and control the decoding circuit to decode the read data when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.

### Claim 14 (depends on 13)

The memory system according to claim 13, wherein
the read of the data is triggered by a read command from the host that designates a logical address of the data, and
the memory controller determines a physical address in the memory chip, mapped to the logical address.