# US 10,373,655 B2 · Apparatuses and methods for providing bias signals according to operation modes as supply voltages vary in a semiconductor device

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- Number: US 10,373,655 B2
- Document ID: US10373655B2
- Status: Granted
- Kind: B2
- Application number: 15/833,643
- Filed: 2017-12-06
- Published: 2019-06-06
- Granted: 2019-08-06
- Earliest claimed: 2017-12-06
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kenji Asaki; Shuichi Tsukada; Sachiko Edo
- Web page: https://patentgrep.com/patent/US10373655B2

## CPC

- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G05F 3/24: wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence)
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1087: {Data input latches}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 29/46: Test trigger logic
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 2029/5004: {Voltage}
- G11C 2029/5006: {Current}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.

## Claims

### Claim 1

An apparatus, comprising:
a power supply line configured to provide a supply voltage; and
a bias circuit coupled to the power supply line to produce a bias current, the bias circuit configured to:
decrease the bias current as the supply voltage increases from a first value to a second value,
continue to decrease the bias current as the supply voltage further increases from the second value in a first operation mode, and
prevent the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein the bias circuit is configured to increase the bias current as the supply voltage further increases from the second value in the second mode.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising:
an additional power supply line configured to provide an additional supply voltage;
first and second nodes;
a first transistor coupled between the power supply line and the first node;
a second transistor coupled between the first and second nodes;
an impedance element coupled between the second node and the additional power supply line; and
a third transistor coupled between the first and second nodes in parallel to the second transistor, the third transistor configured to be in an off state in the first operation mode and in an on state in the second operation mode.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the second transistor is controlled to keep the second node at a first voltage regardless of a value of the supply voltage.

### Claim 5 (depends on 3)

The apparatus of claim 3, further comprising:
a third node;
an additional impedance element coupled between the power supply line and the third node; and
a fourth transistor coupled between the third node and the second node.

### Claim 6 (depends on 3)

The apparatus of claim 3, further comprising a buffer circuit coupled to the first node, the buffer circuit configured to amplify external signals with consumption of a current generated responsively to the bias current.

### Claim 7

An apparatus, comprising:
a bias circuit configured to receive a supply voltage and the bias circuit further configured to provide a bias signal having a magnitude that decreases at a rate to a non-zero minimum magnitude with increasing supply voltage in a first operation mode and to provide the bias signal having a magnitude that decreases at the rate to less than the non-zero minimum magnitude with increasing supply voltage in a second operation mode; and
a buffer circuit configured to receive the bias signal and the supply voltage, and to provide output signals at an output responsive to input data strobe signals provided to an input, the buffer circuit further configured to have a propagation delay from the input to the output that varies with the magnitude of the bias signal.

### Claim 8 (depends on 7)

The apparatus of claim 7 wherein the bias circuit is configured to provide the bias signal having a magnitude that decreases at the rate for increasing supply voltage until the magnitude decreases at the rate to zero.

### Claim 9 (depends on 7)

The apparatus of claim 7 wherein the bias circuit comprises a first transistor configured to provide the bias signal and the buffer circuit comprises a second transistor coupled to the first transistor and configured to provide power based on the bias signal, the first transistor and the second transistor configured as a current mirror.

### Claim 10 (depends on 7)

The apparatus of claim 7 wherein the bias circuit comprises a mode circuit configured to be activated in the first operation mode to set the non-zero minimum magnitude for the bias signal and to be not activated in the second operation mode to not set the non-zero minimum magnitude for the bias signal.

### Claim 11 (depends on 10)

The apparatus of claim 10 wherein the mode circuit comprises a transistor and a resistance coupled in series with the transistor, the transistor configured to be activated in the first operation mode and to not be activated in the second operation mode.

### Claim 12 (depends on 10)

The apparatus of claim 10 wherein the mode circuit is coupled between first and second nodes and the mode circuit further comprises a transistor coupled in parallel to the mode circuit between the first and second nodes, the mode circuit configured to provide a resistive current path between first and second nodes when activated.

### Claim 13 (depends on 12)

The apparatus of claim 12 wherein the bias circuit further comprises a current source configured to receive the supply voltage and to provide an increasing source current to the first node responsive to increasing supply voltage.

### Claim 14 (depends on 13)

The apparatus of claim 13 wherein the current source comprises an adjustable resistance, wherein a resistance of the adjustable resistance sets the rate.

### Claim 15 (depends on 7)

The apparatus of claim 7 wherein the buffer circuit comprises:
a first circuit stage having a first propagation delay that increases responsive to decreasing magnitude of the bias signal; and
a second circuit stage coupled to the first circuit stage and having a second propagation delay that decreases with increasing supply voltage.

### Claim 16 (depends on 7)

The apparatus of claim 7 wherein the bias signal comprises at least one of a bias current and a bias voltage.

### Claim 17

A method, comprising:
varying a bias signal responsive to variations in supply voltage, the bias signal having a minimum current for increasing supply voltage;
changing a propagation delay of a circuit configured to receive the supply voltage based on the bias signal; and
decreasing the bias signal to less than the minimum current for increasing supply voltage to evaluate operation of the circuit.

### Claim 18 (depends on 17)

The method of claim 17 wherein varying the bias signal responsive to variations in supply voltage comprise decreasing a current of the bias signal responsive to increasing supply voltage.

### Claim 19 (depends on 18)

The method of claim 18 wherein changing the propagation delay of the circuit comprises increasing the propagation delay of the circuit for decreasing current of the bias signal.

### Claim 20 (depends on 17)

The method of claim 17 wherein a voltage limit corresponds to the supply voltage at which the bias signal has the minimum current, and wherein the method further comprises increasing the bias signal from the minimum current for increasing supply voltage greater than the voltage limit during normal operation of the bias signal.