# US 10,373,581 B2 · Semiconductor device, and display device and electronic device utilizing the same

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- Number: US 10,373,581 B2
- Document ID: US10373581B2
- Status: Granted
- Kind: B2
- Application number: 16/178,650
- Filed: 2018-11-02
- Published: 2019-06-13
- Granted: 2019-08-06
- Earliest claimed: 2002-12-25
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hajime Kimura; Yutaka Shionoiri
- Web page: https://patentgrep.com/patent/US10373581B2

## CPC

- G09G 5/003: {Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092)}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/36: using liquid crystals
- H03K 19/018507: {Interface arrangements}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

## Claims

### Claim 1

A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor; and
a fourth transistor,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each an N-channel transistor, and
wherein:
one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;
one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor;
the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor;
the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;
the other of the source and the drain of the second transistor is electrically connected to a first wiring;
the other of the source and the drain of the fourth transistor is electrically connected to the first wiring;
a gate of the second transistor is electrically connected to a gate of the fourth transistor;
the other of the source and the drain of the first transistor is electrically connected to a first input terminal;
the gate of the second transistor is electrically connected to a second input terminal; and
the one of the source and the drain of the first transistor is electrically connected to an output terminal.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the other of the source and the drain of the first transistor is configured to be input with a first signal,
wherein the gate of the second transistor is configured to be input with a second signal; and
wherein the one of the source and the drain of the first transistor is configured to output a third signal.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the first wiring is configured to be supplied with a first potential.

### Claim 4

A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor; and
a fourth transistor,
wherein:
one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;
one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor;
the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor;
the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;
the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the first transistor is configured to be input with a first signal; and
a gate of the second transistor is configured to be input with a second signal.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same polarity.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each an N-channel transistor.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4, comprising a gate line driver circuit comprising the first transistor, the second transistor, the third transistor, and the fourth transistor.

### Claim 8

A display device comprising:
a pixel over a substrate; and
a gate line driver circuit over the substrate and configured to output a selection signal to the pixel,
wherein the gate line driver circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, and
wherein:
one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;
one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor;
the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor;
the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;
the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the first transistor is configured to be input with a first signal; and
a gate of the second transistor is configured to be input with a second signal.

### Claim 9 (depends on 8)

The display device according to claim 8,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same polarity.

### Claim 10 (depends on 8)

The display device according to claim 8,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each an N-channel transistor.