# US 10,373,578 B2 · GOA driving circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,578 B2 - Document ID: US10373578B2 - Status: Granted - Kind: B2 - Application number: 15/326,575 - Filed: 2016-12-29 - Published: 2018-11-22 - Granted: 2019-08-06 - Earliest claimed: 2016-11-28 - Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd. - Inventors: Mang Zhao - Web page: https://patentgrep.com/patent/US10373578B2 ## CPC - G09G 3/3677: {suitable for active matrices only} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes - G09G 2330/021: Power management, e.g. power saving - H03K 3/037: Bistable circuits - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Disclosed is a GOA driving circuit, which includes: an input control module, a latch module, a processing module, and a buffer module. A clock control signal is not used to control the input control module, so that the load for generating the clock control signal and power consumption of the circuit can be effectively reduced. ## Claims ### Claim 1 A gate driver on array (GOA) driving circuit, comprising: an input control module, configured to input a cascade signal; a latch module, connected with the input control module and configured to latch the cascade signal input by the input control module; a processing module, connected with the latch module and configured to process the cascade signal output by the latch module into a first intermediate signal; and a buffer module, connected with the processing module and configured to buffer and process the first intermediate signal into a gate driving signal and a second intermediate signal, wherein a phase of the first intermediate signal is opposite to a phase of the second intermediate signal; wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the intermediate signal output by a previous-stage GOA driving circuit or a next-stage GOA driving circuit and the second intermediate signal output by a next-stage GOA driving circuit or a previous-stage GOA driving circuit, or wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the first intermediate signal and the second intermediate signal output by a previous-stage GOA driving circuit and a next-stage GOA driving circuit; and wherein the processing module comprises a NAND gate, a first input end of which is connected to an output end of the latch module, a second input end of which is connected to a first time-sequence driving signal, and an output end of which is connected to the buffer module and outputs the first intermediate signal; wherein the buffer module comprises a third phase inverter, a fourth phase inverter, and a fifth phase inverter that are connected in series, wherein an input end of the third phase inverter is connected to the processing module, and an output end of the third phase inverter is connected to an input end of the fourth phase inverter; wherein an output end of the fourth phase inverter is connected to an input end of the fifth phase inverter, and outputs the second intermediate signal; and wherein an output end of the fifth phase inverter outputs a gate driving signal; wherein the input control module comprises: a first transistor, which is a P type transistor, a gate of which is configured to input the first intermediate signal output by the next-stage GOA driving circuit, a source of which is configured to input a first control signal, and a drain of which is connected to the latch module; and a second transistor, which is an N type transistor, a gate of which is configured to input the second intermediate signal output by the previous-stage GOA driving circuit, a source of which is configured to input a second control signal, and a drain of which is connected to the latch module; wherein the latch module comprises: a first phase inverter, an input end of which is connected to the drains of the first transistor and the second transistor, and an output end of which is connected to the processing module; a third transistor, which is a P type transistor, a gate of which is configured to input the second intermediate signal output by the previous-stage GOA driving circuit, and a drain of which is connected to the input end of the first phase inverter; a fourth transistor, which is an N type transistor, a gate of which is configured to input the first intermediate signal output by the next-stage GOA driving circuit, and a drain of which is connected to a source of the third transistor; and a second phase inverter, an input end of which is connected to the output end of the first phase inverter, and an output end of which is connected to a source of the fourth transistor. ### Claim 2 A date driver on array (GOA) driving circuit, comprising: an input control module, configured to input a cascade signal; a latch module, connected with the input control module and configured to latch the cascade signal input by the input control module; a processing module, connected with the latch module and configured to process the cascade signal output by the latch module into a first intermediate signal; and a buffer module, connected with the processing module and configured to buffer and process the first intermediate signal into a gate driving signal and a second intermediate signal, wherein a phase of the first intermediate signal is opposite to a phase of the second intermediate signal; wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the intermediate signal output by a previous-stage GOA driving circuit or a next-stage GOA driving circuit and the second intermediate signal output by a next-stage GOA driving circuit or a previous-stage GOA driving circuit, or wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the first intermediate signal and the second intermediate signal output by a previous-stage GOA driving circuit and a next-stage GOA driving circuit; and wherein the processing module comprises a NAND gate, a first input end to which is connected to an output end of the latch module, a second input end of which is connected to a first time-sequence driving signal, and an output end of which is connected to the buffer module and outputs the first intermediate signal; wherein the buffer module comprises a third phase inverter, a fourth phase inverter, and a fifth phase inverter that are connected in series, wherein an input end of the third phase inverter is connected to the processing module, and an output end of the third phase inverter is connected to an input end of the fourth phase inverter; wherein an output end of the fourth phase inverter is connected to an input end of the fifth phase inverter, and outputs the second intermediate signal; and wherein an output end of the fifth phase inverter outputs a gate driving signal; wherein the input control module comprises: a first transistor, which is a P type transistor, a gate of which is configured to input the first intermediate signal output by the previous-stage GOA driving circuit, a source of which is configured to input a first control signal, and a drain of which is to connected to the latch module; and a second transistor, which is an N type transistor, a gate of which is configured to input the second intermediate signal output by the next-stage GOA driving circuit, a source of which is configured to input a second control signal, and a drain of which is connected to the latch module; wherein the latch module comprises: a first phase inverter, an input end of which is connected to the drains of the first transistor and the second transistor; a second phase inverter, an input end of which is connected to an output end of the first phase inverter, and an output end of which is connected to the processing module; a third transistor, which is an N type transistor, a gate of which is configured to input the first intermediate signal output by the previous-stage GOA driving circuit, and a drain of which is connected to the input end of the first phase inverter; and a fourth transistor, which is a P type transistor, a gate of which is configured to input the second intermediate signal output by the next-stage GOA driving circuit, a drain of which is connected to a source of the third transistor, and a source of which is connected to the output end of the second phase inverter. ### Claim 3 A gate driver on array (GOA) driving circuit, comprising: an input control module, configured to input a cascade signal; a latch module, connected with the input control module and configured to latch the cascade signal input by the input control module; a processing module, connected with the latch module and configured to process the cascade signal output by the latch module into a first intermediate signal; and a buffer module, connected with the processing module and configured to buffer and process the first intermediate signal into a gate driving signal and a second intermediate signal, wherein a phase of the first intermediate signal is opposite to a phase of the second intermediate signal; wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the intermediate signal output by a previous-stage GOA driving circuit or a next-stage GOA driving circuit and the second intermediate signal output by a next-stage GOA driving circuit or a previous-stage GOA driving circuit, or wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the first intermediate signal and the second intermediate signal output by a previous-stage GOA driving circuit and a next-stage GOA driving circuit; and wherein the processing module comprises a NAND gate, a first input end to which is connected to an output end of the latch module, a second input end of which is connected to a first time-sequence driving signal, and an output end of which is connected to the buffer module and outputs the first intermediate signal; wherein the buffer module comprises a third phase inverter, a fourth phase inverter, and a fifth phase inverter that are connected in series, wherein an input end of the third phase inverter is connected to the processing module, and an output end of the third phase inverter is connected to an input end of the fourth phase inverter; wherein an output end of the fourth phase inverter is connected to an input end of the fifth phase inverter, and outputs the second intermediate signal; and wherein an output end of the fifth phase inverter outputs a gate driving signal; wherein the input control module comprises: a first transistor, which is an N type transistor, a gate of which is configured to input the second intermediate signal output by the previous-stage GOA driving circuit, a source of which is configured to input a second control signal, and a drain of which is connected to the latch module; and a second transistor, which is an N type transistor, a gate of which is configured to input the second intermediate signal output by the next-stage GOA driving circuit, a source of which is configured to input a second control signal, and a drain of which is connected to the latch module; wherein the latch module comprises: a first phase inverter, an input end of which is connected to the drain of the first transistor, and an output end of which is connected to the processing module; a third transistor, which is a P type transistor, a gate of which is configured to input the second intermediate signal output by the previous-stage GOA driving circuit, and a drain of which is connected to the input end of the first phase inverter; a fourth transistor, which is a P type transistor, a gate of which is configured to input the second intermediate signal output by the next-stage GOA driving circuit, and a source of which is connected to the output end of the first phase inverter; and a second phase inverter, an input end of which is connected to a drain of the fourth transistor, and an output end of which is connected to a source of the third transistor. ### Claim 4 A gate driver on array (GOA) driving circuit, comprising: an input control module, configured to input a cascade signal; a latch module, connected with the input control module and configured to latch the cascade signal input by the input control module; a processing module, connected with the latch module and configured to process the cascade signal output by the latch module into a first intermediate signal; and a buffer module, connected with the processing module and configured to buffer and process the first intermediate signal into a gate driving signal and a second intermediate signal, wherein a phase of the first intermediate signal is opposite to a phase of the second intermediate signal; wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the intermediate signal output by a previous-stage GOA driving circuit or a next-stage GOA driving circuit and the second intermediate signal output by a next-stage GOA driving circuit or a previous-stage GOA driving circuit, or wherein the input control module inputs the cascade signal, and the latch module latches the cascade signal input by the input control module under control of the first intermediate signal and the second intermediate signal output by a previous-stage GOA driving circuit and a next-stage GOA driving circuit; and wherein the processing module comprises a NAND gate, a first input end of which is connected to an output end of the latch module, a second input end of which is connected to a first time-sequence driving signal, and an output end of which is connected to the buffer module and outputs the first intermediate signal; wherein the buffer module comprises a third phase inverter, a fourth phase inverter, and a fifth phase inverter that are connected in series, wherein an input end of the third phase inverter is connected to the processing module, and an output end of the third phase inverter is connected to an input end of the fourth phase inverter; wherein an output end of the fourth phase inverter is connected to an input end of the fifth phase inverter, and outputs the second intermediate signal; and wherein an output end of the fifth phase inverter outputs a gate driving signal; wherein the input control module comprises: a first transistor, which is a P type transistor, a gate of which is configured to input the first intermediate signal output by the next-stage GOA driving circuit, a source of which is configured to input a first control signal, and a drain of which is connected to the latch module; and a second transistor, which is a P type transistor, a gate of which is configured to input the first intermediate signal output by the previous-stage GOA driving circuit, a source of which is configured to input a first control signal, and a drain of which is connected to the latch module; wherein the latch module comprises: a first phase inverter, an input end of which is connected to the drain of the first transistor, and am output end of which is connected to the processing module; a third transistor, which is am N type transistor, a gate of which is configured to input the first intermediate signal output by the next-stage GOA driving circuit, and a drain of which is connected to the input end of the first phase inverter; a fourth transistor, which is an N type transistor, a gate of which is configured to input the first intermediate signal output by the previous-stage GOA driving circuit, and a source of which is connected to the output end of the first phase inverter; and a second phase inverter, an input end of which is connected to a drain of the fourth transistor, and an output end of which is connected to a source of the third transistor.