# US 10,373,528 B2 · Cell-level realization of burn after reading for NAND flash

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,528 B2
- Document ID: US10373528B2
- Status: Granted
- Kind: B2
- Application number: 15/379,216
- Filed: 2016-12-14
- Published: 2018-06-14
- Granted: 2019-08-06
- Earliest claimed: 2016-12-14
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Zvonimir Z. Bandic; Robert Eugeniu Mateescu; Minghai Qin; Chao Sun
- Web page: https://patentgrep.com/patent/US10373528B2

## CPC

- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

## Claims

### Claim 1

A method for use with a first memory device comprising a first file and a first bit coupled to a first word line, the first file comprising the first bit, the method comprising:
determining that the first file has been read from the first memory device; and
changing a logic state of the first bit after a first predetermined period of time, wherein the first word line, after changing the logic state, comprises a raw bit error rate that requires for correction an error correction code (ECC) rate of less than 0.9.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first memory device is a single level cell (SLC) memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first memory device is a multi-level cell (MLC) memory device.

### Claim 4 (depends on 3)

The method of claim 3, wherein changing a logic state comprises changing a logic state of a lower page of the MLC.

### Claim 5 (depends on 3)

The method of claim 3, wherein changing a logic state comprises changing a physical state of the first bit to 3.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first memory device further comprises an additional bit coupled to a first word line, the first file comprises the additional bit, and wherein changing a logic state of the first bit additionally includes changing the logic state of the additional bit.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
searching for a predetermined pattern in the first memory device, wherein the predetermined pattern includes at least three bits, wherein a second bit of the three bits is disposed on a second word line separate from the first word line, wherein a third bit of the three bits is disposed on a third word line separate from both the first word line and the second word line and wherein the first word line is disposed between the second word line and the third word line.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first memory device has a raw bit error rate (RBER) of at least 0.0625.

### Claim 9

A computer system for storing and retrieving files, comprising:
a processor; and
a memory system comprising a first memory device that includes a first file and a first bit coupled to a first word line, the first file comprising the first bit, the memory system storing instructions that, when executed by the processor, cause the computer system to:
determine that the first file has been read from the first memory device; and
change a logic state of the first bit after a first predetermined period of time, wherein the first word line, after changing the logic state, comprises a raw bit error rate that requires for correction an error correction code (ECC) rate of less than 0.9.

### Claim 10 (depends on 9)

The computer system of claim 9, wherein the first memory device is an SLC memory device.

### Claim 11 (depends on 9)

The computer system of claim 9, wherein the first memory device is an MLC memory device.

### Claim 12 (depends on 11)

The computer system of claim 11, wherein change a logic state comprises changing a logic state of a lower page of the MLC.

### Claim 13 (depends on 11)

The computer system of claim 11, wherein change a logic state comprises changing a physical state of the first bit to 3.

### Claim 14 (depends on 9)

The computer system of claim 9, wherein the first memory device further comprises an additional bit coupled to a first word line, the first file comprises the additional bit, and wherein change a logic state of the first bit additionally includes changing the logic state of the additional bit.

### Claim 15 (depends on 14)

The computer system of claim 14, further comprising:
searching for a predetermined pattern in the first memory device, wherein the predetermined pattern includes at least three bits, wherein a second bit of the three bits is disposed on a second word line separate from the first word line, wherein a third bit of the three bits is disposed on a third word line separate from both the first word line and the second word line and wherein the first word line is disposed between the second word line and the third word line.

### Claim 16 (depends on 9)

The computer system of claim 9, wherein the first memory device has a raw bit error rate (RBER) of at least 0.0625.

### Claim 17

A non-transitory computer readable storage medium, containing instructions that, when executed by a processor, cause a computer system to burn files after a read process has been completed for a first memory device comprising a first file and a first bit coupled to a first word line, the first file comprising the first bit, by performing the steps of:
determining that the first file has been read from the first memory device; and
changing a logic state of the first bit after a first predetermined period of time, wherein the first word line, after changing the logic state, comprises a raw bit error rate that requires for correction an error correction code (ECC) rate of less than 0.9.

### Claim 18 (depends on 17)

The storage medium of claim 17, wherein the first memory device is an SLC memory device.

### Claim 19 (depends on 17)

The storage medium of claim 17, wherein the first memory device is an MLC memory device.

### Claim 20 (depends on 19)

The storage medium of claim 19, wherein changing a logic state comprises changing a logic state of a lower page of the MLC.

### Claim 21 (depends on 19)

The storage medium of claim 19, wherein changing a logic state comprises changing a physical state of the first bit to 3.

### Claim 22 (depends on 17)

The storage medium of claim 17, wherein the first memory device further comprises an additional bit coupled to a first word line, the first file comprises the additional bit, and wherein changing a logic state of the first bit additionally includes changing the logic state of the additional bit.

### Claim 23 (depends on 22)

The storage medium of claim 22, further comprising:
searching for a predetermined pattern in the first memory device, wherein the predetermined pattern includes at least three bits, wherein a second bit of the three bits is disposed on a second word line separate from the first word line, wherein a third bit of the three bits is disposed on a third word line separate from both the first word line and the second word line and wherein the first word line is disposed between the second word line and the third word line.

### Claim 24 (depends on 17)

The storage medium of claim 17, wherein the first memory device has a raw bit error rate (RBER) of at least 0.0625.

### Claim 25

A first memory device comprising:
a first file and a first bit coupled to a first word line, the first file comprising the first bit;
means for determining that the first file has been read from the first memory device; and
means for changing a logic state of the first bit after a first predetermined period of time, wherein the first word line, after changing the logic state, comprises a raw bit error rate that requires for correction an error correction code (ECC) rate of less than 0.9.

### Claim 26 (depends on 25)

The device of claim 25, wherein the first memory device is a single level cell (SLC) memory device.

### Claim 27 (depends on 25)

The device of claim 25, wherein the first memory device is a multi-level cell (MLC) memory device.

### Claim 28 (depends on 27)

The device of claim 27, wherein changing a logic state comprises changing a logic state of a lower page of the MLC.

### Claim 29 (depends on 27)

The device of claim 27, wherein changing a logic state comprises changing a physical state of the first bit to 3.

### Claim 30 (depends on 25)

The device of claim 25, wherein the first memory device further comprises an additional bit coupled to a first word line, the first file comprises the additional bit, and wherein the means for changing a logic state of the first bit additionally includes means for changing the logic state of the additional bit.

### Claim 31 (depends on 30)

The device of claim 30, further comprising:
means for searching for a predetermined pattern in the first memory device, wherein the predetermined pattern includes at least three bits, wherein a second bit of the three bits is disposed on a second word line separate from the first word line, wherein a third bit of the three bits is disposed on a third word line separate from both the first word line and the second word line and wherein the first word line is disposed between the second word line and the third word line.

### Claim 32 (depends on 25)

The device of claim 25, wherein the first memory device has a raw bit error rate (RBER) of at least 0.0625.