# US 10,373,287 B2 · Fast GPU context switch

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- Number: US 10,373,287 B2
- Document ID: US10373287B2
- Status: Granted
- Kind: B2
- Application number: 15/680,885
- Filed: 2017-08-18
- Published: 2019-02-21
- Granted: 2019-08-06
- Earliest claimed: 2017-08-18
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Tatsuya Iwamoto; Kutty Banerjee; Rohan Sanjeev Patil
- Web page: https://patentgrep.com/patent/US10373287B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.

## Claims

### Claim 1

A graphics processing unit (GPU) task switch operation, comprising:
executing, on a GPU, a first task at a first GPU clock rate, the first task having a first priority;
detecting, during execution of the first task at the first GPU clock rate, a second task scheduled for execution on the GPU, the second task having a second priority that is higher than the first priority;
increasing, in response to detecting the second task, the first GPU clock rate to a second GPU clock rate;
executing, on the GPU, the first task at the second GPU clock rate until a task switch boundary of the first task is reached;
halting execution of the first task in response to reaching the task switch boundary; and
executing, on the GPU, the second task after halting execution of the first task.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second GPU clock rate comprises a maximum GPU clock rate.

### Claim 3 (depends on 2)

The method of claim 2, further comprising increasing an operating voltage of the GPU.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second clock rate is a function of the second priority.

### Claim 5 (depends on 1)

The method of claim 1, wherein the task switch boundary is reached before the first task completes executing.

### Claim 6 (depends on 1)

The method of claim 1, wherein increasing the first GPU clock rate to a second GPU clock rate further comprises increasing an operating frequency of a support element of the GPU.

### Claim 7 (depends on 6)

The method of claim 6, wherein the support element comprises one or more of a memory, a memory controller, and a communication network.

### Claim 8 (depends on 1)

The method of claim 1, wherein executing the second task comprises executing the second task at the second GPU clock rate.

### Claim 9 (depends on 1)

The method of claim 1, wherein executing the second task comprises executing the second task at a third GPU clock rate, wherein the third GPU clock rate is higher than the first GPU clock rate and lower than the second GPU clock rate.

### Claim 10

A non-transitory program storage device, readable by a processor and comprising instructions stored thereon to cause one or more graphics processing units (GPUs) to:
execute, on a GPU, a first task at a first GPU clock rate, the first task having a first priority;
detect, during execution of the first task at the first GPU clock rate, a second task scheduled for execution on the GPU, the second task having a second priority that is higher than the first priority;
increase, in response to detection of the second task, the first GPU clock rate to a second GPU clock rate;
execute, on the GPU, the first task at the second GPU clock rate until a task switch boundary of the first task is reached;
halt execution of the first task in response to reaching the task switch boundary; and
execute, on the GPU, the second task after halting execution of the first task.

### Claim 11 (depends on 10)

The non-transitory program storage device of claim 10, wherein the second GPU clock rate comprises a maximum GPU clock rate.

### Claim 12 (depends on 10)

The non-transitory program storage device of claim 10, wherein the instructions to cause the GPU to increase the first GPU clock rate to a second GPU clock rate further comprise instructions to increase an operating frequency of a support element of the GPU.

### Claim 13 (depends on 12)

The non-transitory program storage device of claim 12, wherein the support element comprises one or more of a memory, a memory controller, and a communication network.

### Claim 14 (depends on 10)

The non-transitory program storage device of claim 10, wherein the instructions to cause the GPU to execute the second task comprise instructions to cause the GPU to execute the second task at the second GPU clock rate.

### Claim 15 (depends on 10)

The non-transitory program storage device of claim 10, wherein the instructions to cause the GPU to execute the second task comprise instructions to cause the GPU to execute the second task at a third GPU clock rate, wherein the third GPU clock rate is higher than the first GPU clock rate and lower than the second GPU clock rate.

### Claim 16

An electronic device, comprising:
a graphics processing unit (GPU);
a memory communicatively coupled to the GPU;
a controller communicatively coupled to the GPU and the memory, the controller configured to execute instructions stored in the memory to—
execute, on the GPU, a first task at a first GPU clock rate, the first task having a first priority;
detect, during execution of the first task at the first GPU clock rate, a second task scheduled for execution on the GPU, the second task having a second priority that is higher than the first priority;
increase, in response to detection of the second task, the first GPU clock rate to a second GPU clock rate;
execute, on the GPU, the first task at the second GPU clock rate until a task switch boundary of the first task is reached;
halt execution of the first task in response to reaching the task switch boundary; and
execute, on the GPU, the second task after halting execution of the first task.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the second GPU clock rate comprises a maximum GPU clock rate.

### Claim 18 (depends on 16)

The electronic device of claim 16, wherein the instructions to cause the GPU to increase the first GPU clock rate to a second GPU clock rate further comprise instructions to increase an operating frequency of a support element of the GPU, wherein the support element is communicatively coupled to the GPU.

### Claim 19 (depends on 18)

The electronic device of claim 18, wherein the support element comprises one or more of the memory, a memory controller, and a communication network.

### Claim 20 (depends on 16)

The electronic device of claim 16, wherein the instructions to cause the GPU to execute the second task comprise instructions to cause the GPU to execute the second task at the second GPU clock rate.

### Claim 21 (depends on 16)

The electronic device of claim 16, wherein the instructions to cause the GPU to execute the second task comprise instructions to cause the GPU to execute the second task at a third GPU clock rate, wherein the third GPU clock rate is higher than the first GPU clock rate and lower than the second GPU clock rate.