# US 10,373,285 B2 · Coarse grain coherency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,285 B2 - Document ID: US10373285B2 - Status: Granted - Kind: B2 - Application number: 15/482,810 - Filed: 2017-04-09 - Published: 2018-10-11 - Granted: 2019-08-06 - Earliest claimed: 2017-04-09 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Joydeep Ray; Altug Koker; James A. Valerio; David Puffer; Abhishek R. Appu; Stephen Junkins - Web page: https://patentgrep.com/patent/US10373285B2 ## CPC - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0815: Cache consistency protocols - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/0888: using selective caching, e.g. bypass - G06T 1/60: Memory management - G06F 2212/1024: Latency reduction - G06F 2212/302: In image processor or graphics adapter - G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device - G06F 2212/65: Details of virtual memory and virtual address translation - G06F 2212/656: Address space sharing - G06F 2212/657: Virtual address space management - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory. ## Claims ### Claim 1 A method on an agent of a heterogeneous processing system, the method comprising: receiving a request to access a virtual memory address from a process executing on the agent; determining if the agent has ownership of a first superline associated with the virtual memory address, the first superline associated with a sub-page memory region spanning multiple cache lines, wherein determining if the agent has ownership of the first superline includes reading an entry for the first superline from an on-die superline directory table cache and reading an entry for the first superline from the on-die superline directory table cache includes reading an ownership bit associated with the agent; accessing the virtual memory address from the agent without triggering a snoop request when the agent has ownership of the first superline; and sending a region snoop request to acquire ownership of the first superline when the agent does not have ownership of the first superline. ### Claim 2 (depends on 1) The method as in claim 1, wherein the agent is a central processing unit. ### Claim 3 (depends on 2) The method as in claim 2, wherein the on-die superline directory table cache is shared between multiple agents, at least one agent including a general-purpose graphics processing unit. ### Claim 4 (depends on 3) The method as in claim 3, wherein determining if the agent has ownership of a first superline includes reading an entry for the first superline from a superline directory table in memory when the entry for the first superline is not stored in the on-die superline directory table cache. ### Claim 5 (depends on 1) The method as in claim 1, wherein the agent is a general-purpose graphics processing unit. ### Claim 6 (depends on 5) The method as in claim 5, wherein determining if the agent has ownership of a first superline includes reading an entry for the first superline from a superline ownership table within memory of the general-purpose graphics processing unit. ### Claim 7 A heterogeneous data processing system comprising: a general-purpose processor including a first cache memory and a first coherency module; a general-purpose graphics processor including a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, the heterogeneous coherency enabled at multiple cache line granularity, wherein data storage for the first cache memory is managed at cache line granularity, coherence for sub-page shared virtual memory allocations cached by the first cache memory and the second cache memory are managed at superline granularity, and the second cache memory is a last level cache shared between the general-purpose processor and the general-purpose graphics processor; and a first memory module to store a superline directory table, the superline directory table to track ownership for each superline owned by the general-purpose processor and the general-purpose graphics processor, wherein each superline is a sub-page address region that spans multiple cache lines of the first cache memory and the second cache memory. ### Claim 8 (depends on 7) The heterogeneous data processing system as in claim 7, the general-purpose graphics processor additionally including a graphics processing compute block to process a workload including graphics or compute operations, the general-purpose graphics processing compute block including multiple compute clusters, each compute cluster including multiple graphics multiprocessors. ### Claim 9 (depends on 8) The heterogeneous data processing system as in claim 8, wherein the workload is a heterogeneous workload including operations to be performed by the general-purpose graphics processing compute block and the general-purpose processor. ### Claim 10 (depends on 7) The heterogeneous data processing system as in claim 7, wherein the first cache memory is a level 3 cache memory. ### Claim 11 (depends on 7) The heterogeneous data processing system as in claim 7, wherein the general-purpose graphics processing device is an add-in card connected to the separate general-purpose processor via a system bus, wherein the add-in card includes memory coupled with the general-purpose graphics processing device. ### Claim 12 (depends on 7) The heterogeneous data processing system as in claim 7, wherein the second cache memory is a last level cache that is shared between the general-purpose graphics processing compute block and the general-purpose processor. ### Claim 13 (depends on 12) The heterogeneous data processing system as in claim 12, additionally including a superline ownership table to store a set of superlines owned by the general-purpose graphics processing device, wherein the superline ownership table includes an entry for each superline in the set of superlines owned by the general-purpose graphics processing device and each entry in the superline ownership table includes a superline tag and a coherency protocol status for the superline. ### Claim 14 (depends on 13) The heterogeneous data processing system as in claim 13, wherein the coherency protocol status is one of modified, exclusive, shared, or invalid and each entry in the superline ownership table additionally includes a valid bit for each cache line within the superline. ### Claim 15 A non-transitory machine-readable medium storing instructions to perform operations on one or more processors of an agent of a heterogeneous processing system, the operations comprising: receiving a request to access a virtual memory address from a process executing on the agent; determining if the agent has ownership of a first superline associated with the virtual memory address, the first superline associated with a sub-page memory region spanning multiple cache lines, wherein determining if the agent has ownership of the first superline includes reading an entry for the first superline from an on-die superline directory table cache and reading an entry for the first superline from the on-die superline directory table cache includes reading an ownership bit associated with the agent; accessing the virtual memory address from the agent without triggering a snoop request when the agent has ownership of the first superline; and sending a region snoop request to acquire ownership of the first superline when the agent does not have ownership of the first superline. ### Claim 16 (depends on 15) The non-transitory machine-readable medium as in claim 15, wherein the agent is a central processing unit. ### Claim 17 (depends on 16) The non-transitory machine-readable medium as in claim 16, wherein the on-die superline directory table cache is shared between multiple agents, at least one agent including a general-purpose graphics processing unit. ### Claim 18 (depends on 17) The non-transitory machine-readable medium as in claim 17, wherein determining if the agent has ownership of a first superline includes reading an entry for the first superline from a superline directory table in memory when the entry for the first superline is not stored in the on-die superline directory table cache. ### Claim 19 (depends on 15) The non-transitory machine-readable medium as in claim 15, wherein the agent is a general-purpose graphics processing unit. ### Claim 20 (depends on 19) The non-transitory machine-readable medium as in claim 19, wherein determining if the agent has ownership of a first superline includes reading an entry for the first superline from a superline ownership table within memory of the general-purpose graphics processing unit.