# US 10,372,868 B2 · Error resilient digital signal processing device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,868 B2 - Document ID: US10372868B2 - Status: Granted - Kind: B2 - Application number: 14/886,877 - Filed: 2015-10-19 - Published: 2016-04-21 - Granted: 2019-08-06 - Earliest claimed: 2014-10-20 - Assignees: Imec Vzw - Applicants: Imec Vzw; Katholieke Universiteit Leuven, KU LEUVEN R&D - Inventors: Yanxiang Huang; Chunshu Li; Meng Li - Web page: https://patentgrep.com/patent/US10372868B2 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/30: Circuit design - H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data. ## Claims ### Claim 1 A signal processing device comprising: a computation circuit configured to use clocked input data to generate first data corresponding to a first clock cycle; a logic circuit configured to generate a control signal indicating whether the signal processing device exhibited a timing error during the first clock cycle; a selection circuit configured to receive the control signal and, based on whether the control signal indicates that the signal processing device exhibited the timing error during the first clock cycle, provide as output, during a transition from the first clock cycle to a second clock cycle, either the first data or second data that is generated by the computation circuit and corresponds to the second clock cycle; a counter configured to count a number of performed computations by the signal processing device according to the control signal and to provide a signal representative of the counted computations; and a circuit configured to clock the input data and provide the clocked input data, wherein the circuit comprises a plurality of timing error detection circuits, wherein each timing error detection circuit is configured to receive one bit of the input data and to provide a local set-up timing error signal if a difference between the one bit of the input data and a clock signal is detected. ### Claim 2 (depends on 1) The signal processing device as in claim 1, wherein the computation circuit comprises at least two computation unit circuits connected in series, the at least two computation unit circuits being configured to perform respective computations of an iteration to generate the first data. ### Claim 3 (depends on 1) The signal processing device as in claim 1, wherein the control signal indicates how many iterations are to be performed by the computation circuit. ### Claim 4 (depends on 3) The signal processing device as in claim 3, wherein the control signal is masked with a signal indicating a last computation cycle. ### Claim 5 (depends on 1) The signal processing device as in claim 1, wherein each timing error detection circuit is further configured to receive a plurality of delayed versions of the clock signal, each of the delayed versions having a different timing offset with respect to the other, and to provide a multi-bit local set-up timing error signal. ### Claim 6 (depends on 1) The signal processing device as in claim 1, wherein the logic circuit is configured to receive the local set-up timing error signals from each of the timing error detection circuits and to provide the control signal. ### Claim 7 (depends on 1) The signal processing device as in claim 1, wherein the computation circuit is an iterative-based computation circuit. ### Claim 8 (depends on 1) A device comprising a signal processing device as in claim 1. ### Claim 9 (depends on 8) A system comprising a device as in claim 8. ### Claim 10 A method performed by a signal processing device, the method comprising: using, by a computation circuit of the signal processing device, clocked input data to generate first data corresponding to a first clock cycle; generating, by a logic circuit of the signal processing device, a control signal indicating whether the signal processing device exhibited a timing error during the first clock cycle; receiving, by a selection circuit of the signal processing device, the control signal; based on whether the control signal indicates that the signal processing device exhibited the timing error during the first clock cycle, providing as output, during a transition from the first clock cycle to a second clock cycle, either the first data or second data that is generated by the computation circuit and corresponds to the second clock cycle; counting a number of performed computations by the signal processing device according to the control signal and providing a signal representative of the counted computations; clocking the input data and providing the clocked input data; and receiving one bit of the input data and providing a local set-up timing error signal if a difference between the one bit of the input data and a clock signal is detected. ### Claim 11 (depends on 10) The method as in claim 10, wherein the control signal indicates how many iterations are to be performed by the signal processing device.