# US 10,372,867 B2 · In-design real-time electrical impact verification flow

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- Number: US 10,372,867 B2
- Document ID: US10372867B2
- Status: Granted
- Kind: B2
- Application number: 14/843,982
- Filed: 2015-09-02
- Published: 2017-03-02
- Granted: 2019-08-06
- Earliest claimed: 2014-09-02
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Jun Wang; Randy Bishop; Jingyu Xu; Dick Liu; Hu Cai; Jun Lu
- Web page: https://patentgrep.com/patent/US10372867B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.

## Claims

### Claim 1

A computer-implemented method of generating a layout of an integrated circuit design, the method comprising:
performing, using a processor, a pre-layout simulation of the integrated circuit design to generate simulation data;
extracting, using the processor, characteristics of a plurality of routed interconnections based on layout data of the circuit, wherein the layout data comprises extracted spacing and density information of those regions of the circuit for which layout has been finished and estimated spacing and density information of those regions of the circuit for which layout has not yet been finished;
using the simulation data and the extracted characteristics of routed interconnections, calculating, using the processor, an electro-migration (EM) and IR drop for each routed interconnection of the plurality of interconnections; and
creating, using the processor, a modified layout of the integrated circuit by changing, using the processor, the layout of the integrated circuit in accordance with electro-migration (EM) and IR drop limits.

### Claim 2 (depends on 1)

The method of claim 1, wherein the pre-layout simulation data comprise profiles of current or voltages of a plurality of nets of the integrated circuit.

### Claim 3 (depends on 2)

The method of claim 2, wherein the profiles of current or voltages are over at least one of the time domain or the frequency domain.

### Claim 4 (depends on 1)

The method of claim 1, wherein the pre-layout simulation data comprises static current values.

### Claim 5 (depends on 1)

The method of claim 1, wherein the simulation data comprises a value of one or more currents of at least one routed interconnection.

### Claim 6 (depends on 5)

The method of claim 5, wherein the value is one of an average current, an rms current, or a peak current.

### Claim 7 (depends on 1)

The method of claim 1, wherein the simulation data comprises a value of a voltage drop of the at least one routed interconnection.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
automatically rerouting, using the processor, the routed interconnections in accordance with the electro-migration (EM) and IR drop limits, wherein routing parameters for rerouting the routed interconnections are modified prior to rerouting.

### Claim 9

A system for generating a layout of an integrated circuit design, the system configured to:
perform a pre-layout simulation of the integrated circuit design to generate simulation data;
extract characteristics of routed interconnections based on layout data of the circuit, wherein the layout data comprises extracted spacing and density information of those regions of the circuit for which layout has been finished and estimated spacing and density information of those regions of the circuit for which layout has not yet been finished;
using the simulation data and the extracted characteristics, calculate an electro-migration (EM) and IR drop for each routed interconnection; and
create a modified layout of the integrated circuit by changing the layout of the integrated circuit in accordance with electro-migration (EM) and IR drop limits.

### Claim 10 (depends on 9)

The system of claim 9, wherein the pre-layout simulation data comprises profiles of current or voltages of a plurality of nets of the integrated circuit design.

### Claim 11 (depends on 10)

The system of claim 10, wherein the profiles of current or voltages are over at least one of the time domain or the frequency domain.

### Claim 12 (depends on 11)

The system of claim 11, wherein the pre-layout simulation data comprises static current values.

### Claim 13 (depends on 11)

The system of claim 11, wherein the data comprises a value of one or more currents of at least one routed interconnection.

### Claim 14 (depends on 13)

The system of claim 13, wherein the value is one of an average current, an rms current, or a peak current.

### Claim 15 (depends on 9)

The system of claim 9, wherein the simulation data comprises a value of a voltage drop of the at least one routed interconnection.

### Claim 16 (depends on 9)

The system of claim 9 wherein the system is further configured to:
automatically reroute the routed interconnections in accordance with the electro-migration (EM) and IR drop limits, wherein routing parameters for rerouting the routed interconnections are modified prior to rerouting.