# US 10,372,866 B2 · Data processing system to implement wiring/silicon blockages via parameterized cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,866 B2 - Document ID: US10372866B2 - Status: Granted - Kind: B2 - Application number: 15/431,061 - Filed: 2017-02-13 - Published: 2018-08-16 - Granted: 2019-08-06 - Earliest claimed: 2017-02-13 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Christopher J. Berry; Adam R. Jatkowski; Frank Malgioglio; Ryan M. Nett; Joseph J. Palumbo; Sean Salisbury; Gerald L. Strevig, III - Web page: https://patentgrep.com/patent/US10372866B2 ## CPC - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 2111/04: Constraint-based CAD - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC. ## Claims ### Claim 1 A data processing system configured to implement wiring/silicon blockages via parameterized cells (pCells), the data processing system comprising: a front end-of-line placement/blockage (FEOL P/B) controller configured to generate at least one placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC), and outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the at least one placement blockage; a back end-of-line wiring track (BEOL WT) controller in signal communication with the FEOL P/B controller, the BEOL WT controller configured to generate a wire track blockage of the IC; and a BEOL power track (BEOL PT) controller in signal communication with the BEOL WT controller, the BEOL PT controller configured to generate a metal blockage within the wire track blockage; wherein a combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC, and wherein the concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC is provided for manufacturing the IC, and wherein the parent-child contract indicates placement of the child block with respect to a larger parent block, the child block including at least one circuit that is physically contained within bounds of the parent block. ### Claim 2 (depends on 1) The data processing system of claim 1, wherein the input parameter includes at least one of a height parameter, a width parameter, and a ceiling parameter. ### Claim 3 (depends on 1) The data processing system of claim 1, wherein the BEOL WT controller generates a horizontal wire track blockage and a vertical wire track blockage extending perpendicular to the horizontal wire track blockage. ### Claim 4 (depends on 3) The data processing system of claim 3, wherein the BEOL WT controller determines a number of horizontal layers and a number of vertical layers based on the placement blockage parameter stored in the wire track allocation database. ### Claim 5 (depends on 4) The data processing system of claim 4, wherein the BEOL WT controller determines whether at least one of the horizontal wire track blockage and the vertical wire track blockage is a multi-patterned layer. ### Claim 6 (depends on 5) The data processing system of claim 5, wherein the BEOL WT controller generates a wire track blockage for each sub-layer included in the multi-patterned layer. ### Claim 7 (depends on 1) The data processing system of claim 1, wherein generating the metal blockage includes generating power terminals having specified dimensions, pitch and connectivity. ### Claim 8 A method of implementing wiring/silicon blockages via parameterized cells (pCells), the method comprising: generating, via a front end-of-line placement/blockage (FEOL P/B) controller, at least one placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC); outputting a placement blockage parameter indicating the at least one placement blockage and storing the at least one placement blockage in a wire track allocation database; generating, via a back end-of-line wiring track (BEOL WT) controller, a wire track blockage of the IC; generating, via a BEOL power track (BEOL PT) controller, a metal blockage within the wire track blockage; and defining a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC based on a combination of the metal blockage and wire track blockage, wherein the concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC is provided for manufacturing the IC, and wherein the parent-child contract indicates placement of the child block with respect to a larger parent block, the child block including at least one circuit that is physically contained within bounds of the parent block. ### Claim 9 (depends on 8) The method of claim 8, wherein the input parameter includes at least one of a height parameter, a width parameter, and a ceiling parameter. ### Claim 10 (depends on 8) The method of claim 8, further comprising generating, via the BEOL WT controller, a horizontal wire track blockage and a vertical wire track blockage extending perpendicular to the horizontal wire track blockage. ### Claim 11 (depends on 10) The method of claim 10, further comprising determining, via the BEOL WT controller, a number of horizontal layers and a number of vertical layers based on the placement blockage parameter stored in the wire track allocation database. ### Claim 12 (depends on 11) The method of claim 11, further comprising determining, via the BEOL WT controller, whether at least one of the horizontal wire track blockage and the vertical wire track blockage is a multi-patterned layer. ### Claim 13 (depends on 12) The method of claim 12, further comprising generating, via the BEOL WT controller, a wire track blockage for each sub-layer included in the multi-patterned layer. ### Claim 14 (depends on 8) The method of claim 8, further comprising generating, via the BEOL PT controller, power terminals having specified dimensions, pitch and connectivity based on the metal blockage. ### Claim 15 A computer program product configured to implement wiring/silicon blockages via parameterized cells (pCells), the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic pCell processor to cause the pCell processor to: generate, via a front end-of-line placement/blockage (FEOL P/B) controller, at least one placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC); output a placement blockage parameter indicating the at least one placement blockage and store the at least one placement blockage in a wire track allocation database; generate, via a back end-of-line wiring track (BEOL WT) controller, a wire track blockage of the IC; generate, via a BEOL power track (BEOL PT) controller, a power pin within the wire track blockage; and define a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC based on a combination of the metal blockage and wire track blockage, wherein the concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC is provided for manufacturing the IC, and wherein the parent-child contract indicates placement of the child block with respect to a larger parent block, the child block including at least one circuit that is physically contained within bounds of the parent block. ### Claim 16 (depends on 15) The computer program product of claim 15, wherein the input parameter includes at least one of a height parameter, a width parameter, and a ceiling parameter. ### Claim 17 (depends on 15) The computer program product of claim 15, wherein the pCell processor to commands the BEOL WT controller to generate a horizontal wire track blockage and a vertical wire track blockage extending perpendicular to the horizontal wire track blockage. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein the pCell processor to commands the BEOL WT controller to determine a number of horizontal layers and a number of vertical layers based on the placement blockage parameter stored in the wire track allocation database. ### Claim 19 (depends on 18) The computer program product of claim 18, wherein the pCell processor to commands the BEOL WT controller to determine whether at least one of the horizontal wire track blockage and the vertical wire track blockage is a multi-patterned layer. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein the pCell processor to commands the BEOL WT controller to generate a wire track blockage for each sub-layer included in the multi-patterned layer, and wherein the pCell processor to commands the BEOL PT controller to generate power terminals having specified dimensions, pitch and connectivity based on the metal blockage.