# US 10,372,864 B2 · Global routing in circuit design

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- Number: US 10,372,864 B2
- Document ID: US10372864B2
- Status: Granted
- Kind: B2
- Application number: 15/293,512
- Filed: 2016-10-14
- Published: 2018-04-19
- Granted: 2019-08-06
- Earliest claimed: 2016-10-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Karsten Muuss
- Web page: https://patentgrep.com/patent/US10372864B2

## CPC

- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method includes receiving a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets, generating a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets, calculating a sum of the number of pins, calculating a sum of the length of the nets, identifying a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value, determining the bounding box maximum of the identified net, calculating a tile size as a function of the bounding box maximum, performing a global routing process using the calculated tile size to generate a global routing design.

## Claims

### Claim 1

A method for fabricating an integrated circuit on a wafer, the method comprising:
receiving a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets;
generating a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets;
calculating a sum of the number of pins;
calculating a sum of the length of the nets;
identifying a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value;
determining the bounding box maximum dimension of the identified net;
calculating a tile size as a function of the bounding box maximum dimension;
performing a global routing process using the calculated tile size to generate a global routing design; and
using the global routing design to fabricate an integrated circuit on a wafer.

### Claim 2 (depends on 1)

The method of claim 1, wherein each net of the nets includes a pin.

### Claim 3 (depends on 1)

The method of claim 1, wherein the bounding box maximum dimension is the sum of the maximum length of two sides of a bounding box, where a bounding box of a net is a smallest rectangular area that contains all pins of the net.

### Claim 4 (depends on 1)

The method of claim 1, wherein the net length is a minimal length of a set of conductive lines that connect all of the pins in a net.

### Claim 5 (depends on 1)

The method of claim 1, wherein a pin includes a connection node between a conductive line and a logic device.

### Claim 6 (depends on 1)

The method of claim 1, wherein the tile size is a size of a plurality of tiles used to perform the global routing process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the global routing design includes a route of a conductive line that connects pins of the nets.

### Claim 8

A system for fabricating an integrated circuit on a wafer, comprising:
a memory; and
a processor operative to:
receive a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets;
generate a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets;
calculate a sum of the number of pins;
calculate a sum of the length of the nets;
identify a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value;
determine the bounding box maximum dimension of the identified net;
calculate a tile size as a function of the bounding box maximum dimension;
perform a global routing process using the calculated tile size to generate a global routing design; and
fabricate the integrated circuit based on the global routing design.

### Claim 9 (depends on 8)

The system of claim 8, wherein each net of the nets includes a pin.

### Claim 10 (depends on 8)

The system of claim 8, wherein the bounding box maximum dimension is the sum of the maximum length of two sides of a bounding box, where a bounding box of a net is a smallest rectangular area that contains all pins of the net.

### Claim 11 (depends on 8)

The system of claim 8, wherein the net length is a minimal length of a set of conductive lines that connect all of the pins in a net.

### Claim 12 (depends on 8)

The system of claim 8, wherein a pin includes a connection node between a conductive line and a logic device.

### Claim 13 (depends on 8)

The system of claim 8, wherein the tile size is a size of a plurality of tiles used to perform the global routing process.

### Claim 14 (depends on 8)

The system of claim 8, wherein the global routing design includes a route of a conductive line that connects pins of the nets.

### Claim 15

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method for fabricating an integrated circuit on a wafer, comprising:
receiving a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets;
generating a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets;
calculating a sum of the number of pins;
calculating a sum of the length of the nets;
identifying a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value;
determining the bounding box maximum dimension of the identified net;
calculating a tile size as a function of the bounding box maximum dimension;
performing a global routing process using the calculated tile size to generate a global routing design; and
using the global routing design to fabricate an integrated circuit on a wafer.

### Claim 16 (depends on 15)

The computer readable storage medium of claim 15, wherein each net of the nets includes a pin.

### Claim 17 (depends on 15)

The computer readable storage medium of claim 15, wherein the bounding box maximum dimension is the sum of the maximum length of two sides of a bounding box, where a bounding box of a net is a smallest rectangular area that contains all pins of the net.

### Claim 18 (depends on 15)

The computer readable storage medium of claim 15, wherein the net length is a minimal length of a set of conductive lines that connect all of the pins in a net.

### Claim 19 (depends on 15)

The computer readable storage medium of claim 15, wherein a pin includes a connection node between a conductive line and a logic device.

### Claim 20 (depends on 15)

The computer readable storage medium of claim 15, wherein the tile size is a size of a plurality of tiles used to perform the global routing process.