# US 10,372,863 B2 · Tool for modular circuit board design > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,863 B2 - Document ID: US10372863B2 - Status: Granted - Kind: B2 - Application number: 16/106,584 - Filed: 2018-08-21 - Published: 2018-12-13 - Granted: 2019-08-06 - Earliest claimed: 2016-11-18 - Assignees: Arch Systems Inc. - Applicants: Arch Systems Inc. - Inventors: Timothy Matthew Burke; Christopher Ling - Web page: https://patentgrep.com/patent/US10372863B2 ## CPC - H05K 3/0005: {for designing circuits by computer} - G06F 30/30: Circuit design - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H05K 3/306: with lead-in-hole components (H05K3/32 takes precedence) - H05K 3/368: {parallel to each other (H05K3/361 takes precedence)} - G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules - G06F 2115/12: Printed circuit boards [PCB] or multi-chip modules [MCM] - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - H05K 1/0286: {Programmable, customizable or modifiable circuits (by programmable non-printed jumper connections H05K3/222)} - Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation. ## Claims ### Claim 1 A method for electronic circuit generation, comprising: receiving a first hierarchical circuit representation comprising a first plurality of electronic component nodes associated with a first component layer and a first plurality of electrical conductor nodes associated with a first metal layer; receiving a second hierarchical circuit representation comprising a second plurality of electronic component nodes associated with a second component layer and a second plurality of electrical conductor nodes associated with a second metal layer; and generating a unified hierarchical circuit representation comprising: a first module comprising a first module root node, a second module comprising a second module root node, a unified component layer, and a unified metal layer; wherein generating the unified hierarchical circuit representation comprises: for each electronic component node of the first plurality of electronic component nodes: generating a respective electronic component node associated with the unified component layer, wherein the first module root node is an ancestor node of the respective electronic component node; for each electrical conductor node of the first plurality of electrical conductor nodes: generating a respective electrical conductor node associated with the unified metal layer, wherein the first module root node is an ancestor node of the respective electrical conductor node; for each electronic component node of the second plurality of electronic component nodes: generating a respective electronic component node associated with the unified component layer, wherein the second module root node is an ancestor node of the respective electronic component node; and for each electrical conductor node of the second plurality of electrical conductor nodes: generating a respective electrical conductor node associated with the unified metal layer, wherein the second module root node is an ancestor node of the respective electrical conductor node. ### Claim 2 (depends on 1) The method of claim 1, further comprising: providing electronic device fabrication instructions based on the unified hierarchical circuit representation. ### Claim 3 (depends on 1) The method of claim 1, wherein: a first electronic component node of the first module is associated with a first bounding box at a first location; a second electronic component node of the first module is associated with a second bounding box at a second location; and a first electrical conductor node of the first module is associated with a first line region connecting the first bounding box to the second bounding box. ### Claim 4 (depends on 1) The method of claim 1, further comprising generating a monolithic integrated circuit representation based on the unified hierarchical circuit representation, wherein: the unified hierarchical circuit representation comprises a discrete component node associated with a plurality of circuit elements; and generating the monolithic integrated circuit representation comprises, based on the discrete component node, generating an integrated circuit component node comprising a representation of the plurality of circuit elements. ### Claim 5 (depends on 4) The method of claim 4, wherein the discrete component node is associated with a discrete op-amp component. ### Claim 6 (depends on 1) The method of claim 1, wherein: the first hierarchical circuit representation further comprises a line node, the line node associated with a routing layer and a first module perimeter; and generating the unified hierarchical circuit representation further comprises deleting the routing layer and associating the line node with an ink layer. ### Claim 7 (depends on 1) The method of claim 1, further comprising: determining a first module power requirement and a second module power requirement; and selecting a power module based on the first module power requirement and the second module power requirement; wherein the unified hierarchical circuit representation further comprises the power module. ### Claim 8 (depends on 1) The method of claim 1, wherein: each electronic component node of the first and second pluralities of electronic component nodes is associated with a respective component parameter; and for each electronic component node of the first and second pluralities of electronic component nodes, the respective electronic component node associated with the unified component layer is associated with the respective component parameter. ### Claim 9 (depends on 8) The method of claim 8, wherein: a first electronic component node of the first module is associated with an electrical property value and a first tolerance requirement; and a second electronic component node of the first module is associated with the electrical property value and a second tolerance requirement more restrictive than the first tolerance requirement; the method further comprising generating a bill of materials based on the unified hierarchical circuit representation, comprising: determining an identifier of a physical component having an electrical property substantially equal to the electrical property value and a tolerance satisfying the second tolerance requirement; and adding the identifier to the bill of materials in association with the first electronic component node and the second electronic component node. ### Claim 10 (depends on 9) The method of claim 9, wherein the electrical property value is selected from the group consisting of: a resistance value, a capacitance value, and an inductance value. ### Claim 11 (depends on 1) The method of claim 1, further comprising: fabricating an electronic device based on the unified hierarchical circuit representation. ### Claim 12 (depends on 1) The method of claim 1, further comprising: determining fabrication instructions, based on the unified hierarchical circuit representation, for a unified electronic device; and providing the fabrication instructions to a circuit fabricator. ### Claim 13 (depends on 1) The method of claim 1, wherein a unified electronic device associated with the unified hierarchical circuit representation is fabricated. ### Claim 14 A method for electronic circuit generation, comprising: receiving a first circuit representation comprising a first plurality of electronic component objects and a first plurality of electrical conductor objects; receiving a second circuit representation comprising a second plurality of electronic component objects and a second plurality of electrical conductor objects; and generating a unified hierarchical circuit representation comprising: a first module and a second module; wherein generating the unified hierarchical circuit representation comprises: for each electronic component object of the first plurality of electronic component objects: generating a respective electronic component object of the unified hierarchical circuit representation, the respective electronic component object associated with the first module; for each electrical conductor object of the first plurality of electrical conductor objects: generating a respective electrical conductor object of the unified hierarchical circuit representation, the respective electrical conductor object associated with the first module; for each electronic component object of the second plurality of electronic component objects: generating a respective electronic component object of the unified hierarchical circuit representation, the respective electronic component object associated with the second module; and for each electrical conductor object of the second plurality of electrical conductor objects: generating a respective electrical conductor object of the unified hierarchical circuit representation, the respective electrical conductor object associated with the second module. ### Claim 15 (depends on 14) The method of claim 14, further comprising: receiving a first virtual electronic circuit represented in a first proprietary electrical CAD format; receiving a second virtual electronic circuit represented in a second proprietary electrical CAD format different from the first proprietary electrical CAD format; generating the first circuit representation based on the first virtual electronic circuit; and generating the second circuit representation based on the second virtual electronic circuit. ### Claim 16 (depends on 14) The method of claim 14, further comprising: determining a first value, associated with the first module, of a module parameter; determining a second value, associated with the second module, of the module parameter; and selecting an auxiliary module based on the first value and the second value; wherein the unified hierarchical circuit representation further comprises the processing module. ### Claim 17 (depends on 16) The method of claim 16, wherein: the module parameter is associated with a module computing requirement; and the auxiliary module is a computing module. ### Claim 18 (depends on 14) The method of claim 14, wherein: the first circuit representation defines a first spatial arrangement; the second circuit representation defines a second spatial arrangement; the first module defines a first module spatial arrangement substantially geometrically similar to the first spatial arrangement; and the second module defines a second module spatial arrangement substantially geometrically similar to the second spatial arrangement. ### Claim 19 (depends on 14) The method of claim 14, further comprising fabricating a tile assembly based on the unified hierarchical circuit representation, comprising: fabricating a first PCB assembly associated with the first module, the first PCB assembly comprising a first PCB, a first plurality of electronic components associated with the first plurality of electronic component objects, and a first mounting mechanism; fabricating a second PCB assembly associated with the second module, the second PCB assembly comprising a second PCB, a second plurality of electronic components associated with the second plurality of electronic component objects, and a second mounting mechanism; and attaching the first and second mounting mechanisms to a carrier, wherein a first electronic component of the first plurality of electronic components is electrically coupled to a second electronic component of the second plurality of electronic components via the carrier. ### Claim 20 (depends on 14) The method of claim 14, further comprising: selecting a set of physical components, comprising, for each electronic component object of the unified hierarchical circuit representation, selecting a respective physical component; and fabricating a unified electronic device based on the unified hierarchical circuit representation, wherein the unified electronic device comprises the set of physical components. ### Claim 21 (depends on 20) The method of claim 20, wherein the set of physical components comprises a plurality of discrete components. ### Claim 22 (depends on 21) The method of claim 21, further comprising generating instructions for fabrication of a monolithic integrated circuit based on the unified hierarchical circuit representation. ### Claim 23 (depends on 22) The method of claim 22, wherein: each discrete component of the plurality is associated with a respective component property value; and the instructions for fabrication of the monolithic integrated circuit comprise, for each discrete component of the plurality, instructions for fabrication of a corresponding IC element associated with the respective component property value.