# US 10,372,860 B2 · Netlist abstraction for circuit design floorplanning > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,860 B2 - Document ID: US10372860B2 - Status: Granted - Kind: B2 - Application number: 14/789,787 - Filed: 2015-07-01 - Published: 2017-01-05 - Granted: 2019-08-06 - Earliest claimed: 2015-07-01 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Balkrishna R. Rashingkar; Leonardus J. van Bokhoven; Peiqing Zou - Web page: https://patentgrep.com/patent/US10372860B2 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block. ## Claims ### Claim 1 A method, comprising: using one or more processors of a computing system to create a netlist abstraction based on a netlist of a circuit design, wherein the netlist is divided into a top-level portion and a set of physical blocks, and wherein creating the netlist abstraction comprises: creating a top-level netlist abstraction based on the top-level portion of the netlist; for each physical block in the set of physical blocks, creating a physical block netlist abstraction based on a portion of the netlist that is in the physical block, wherein the physical block netlist abstraction retains macros that are in the physical block; and retaining (1) connectivity information between objects in the netlist abstraction, (2) blockage information that identifies blockages for floorplanning operations, (3) move bound information which specifies spatial boundaries within which objects in the netlist abstraction must be placed, and (4) power domain information which specifies power domains associated with objects in the netlist abstraction; loading the netlist abstraction into a memory of the computing system, wherein the netlist abstraction provides full-chip context of the circuit design for performing floorplanning operations; and performing floorplanning operations on the netlist abstraction to create a floorplan for the circuit design. ### Claim 2 (depends on 1) The method of claim 1, wherein the floorplanning operations comprise macro placement which determines physical locations for macros in the circuit design. ### Claim 3 (depends on 1) The method of claim 1, wherein the top-level netlist abstraction and the physical block netlist abstraction for each physical block in the set of physical blocks are created independently of one another, and wherein said retaining connectivity information between objects in the netlist abstraction comprises retaining connectivity information between ports of the top-level netlist abstraction and physical block netlist abstractions corresponding to the set of physical blocks. ### Claim 4 (depends on 1) The method of claim 1, wherein at least one physical block netlist abstraction comprises a logical netlist abstraction corresponding to a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein the LH node encompasses a macro in the physical block. ### Claim 5 (depends on 1) The method of claim 1, wherein retaining connectivity information between objects in the netlist abstraction comprises: performing tracing on the netlist of the circuit design to identify electrical connections between macros and one or more logical netlist abstractions; and retaining the identified electrical connections. ### Claim 6 (depends on 1) The method of claim 1, wherein the top-level netlist abstraction comprises one or more logical netlist abstractions, wherein each logical netlist abstraction corresponds to a portion of the netlist that is below a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein each logical netlist abstraction comprises a center object that is electrically connected to a set of satellite objects, and wherein each satellite object corresponds to a port of the LH node; and wherein each physical block netlist abstraction comprises one or more logical netlist abstractions, wherein each logical netlist abstraction corresponds to a portion of the netlist that is below a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein each logical netlist abstraction comprises a center object that is electrically connected to a set of satellite objects, and wherein each satellite object corresponds to a port of the LH node. ### Claim 7 A non-transitory computer-readable storage medium storing instructions that, when executed by a computing system, cause the computing system to perform a method comprising: creating a netlist abstraction based on a netlist of a circuit design, wherein the netlist is divided into a top-level portion and a set of physical blocks, and wherein said creating the netlist abstraction comprises: creating a top-level netlist abstraction based on the top-level portion of the netlist; for each physical block in the set of physical blocks, creating a physical block netlist abstraction based on a portion of the netlist that is in the physical block, wherein the physical block netlist abstraction retains macros that are in the physical block; and retaining (1) connectivity information between objects in the netlist abstraction, (2) blockage information that identifies blockages for floorplanning operations, (3) move bound information which specifies spatial boundaries within which objects in the netlist abstraction must be placed, and (4) power domain information which specifies power domains associated with objects in the netlist abstraction; loading the netlist abstraction into a memory of the computing system, wherein the netlist abstraction provides full-chip context of the circuit design for performing floorplanning operations; and performing floorplanning operations on the netlist abstraction to create a floorplan for the circuit design. ### Claim 8 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the floorplanning operations comprise macro placement which determines physical locations for macros in the circuit design. ### Claim 9 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the top-level netlist abstraction and the physical block netlist abstraction for each physical block in the set of physical blocks are created independently of one another, and wherein said retaining connectivity information between objects in the netlist abstraction comprises retaining connectivity information between ports of the top-level netlist abstraction and physical block netlist abstractions corresponding to the set of physical blocks. ### Claim 10 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein at least one physical block netlist abstraction comprises a logical netlist abstraction corresponding to a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein the LH node encompasses a macro in the physical block. ### Claim 11 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein retaining connectivity information between objects in the netlist abstraction comprises: performing tracing on the netlist of the circuit design to identify electrical connections between macros and one or more logical netlist abstractions; and retaining the identified electrical connections. ### Claim 12 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the top-level netlist abstraction comprises one or more logical netlist abstractions, wherein each logical netlist abstraction corresponds to a portion of the netlist that is below a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein each logical netlist abstraction comprises a center object that is electrically connected to a set of satellite objects, and wherein each satellite object corresponds to a port of the LH node; and wherein each physical block netlist abstraction comprises one or more logical netlist abstractions, wherein each logical netlist abstraction corresponds to a portion of the netlist that is below a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein each logical netlist abstraction comprises a center object that is electrically connected to a set of satellite objects, and wherein each satellite object corresponds to a port of the LH node. ### Claim 13 An apparatus, comprising: one or more processors; and a non-transitory storage medium storing instructions that, when executed by the one or more processors, cause the apparatus to perform a method comprising: creating a netlist abstraction based on a netlist of a circuit design, wherein the netlist is divided into a top-level portion and a set of physical blocks, and wherein said creating the netlist abstraction comprises: creating a top-level netlist abstraction based on a top-level portion of the netlist; for each physical block in the set of physical blocks, creating a physical block netlist abstraction based on a portion of the netlist that is in the physical block, wherein the physical block netlist abstraction retains macros that are in the physical block; and retaining (1) connectivity information between objects in the netlist abstraction, (2) blockage information that identifies blockages for floorplanning operations, (3) move bound information which specifies spatial boundaries within which objects in the netlist abstraction must be placed, and (4) power domain information which specifies power domains associated with objects in the netlist abstraction; loading the netlist abstraction into a memory of the apparatus, wherein the netlist abstraction provides full-chip context of the circuit design for floorplanning operations; and performing floorplanning operations on the netlist abstraction to create a floorplan for the circuit design. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the floorplanning operations comprise macro placement which determines physical locations for macros in the circuit design. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the top-level netlist abstraction and the physical block netlist abstraction for each physical block in the set of physical blocks are created independently of one another, and wherein said retaining connectivity information between objects in the netlist abstraction comprises retaining connectivity information between ports of the top-level netlist abstraction and physical block netlist abstractions corresponding to the set of physical blocks. ### Claim 16 (depends on 13) The apparatus of claim 13, wherein at least one physical block netlist abstraction comprises a logical netlist abstraction corresponding to a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein the LH node encompasses a macro in the physical block. ### Claim 17 (depends on 13) The apparatus of claim 13, wherein retaining connectivity information between objects in the netlist abstraction comprises: performing tracing on the netlist of the circuit design to identify electrical connections between macros and one or more logical netlist abstractions; and retaining the identified electrical connections. ### Claim 18 (depends on 13) The apparatus of claim 13, wherein the top-level netlist abstraction comprises one or more logical netlist abstractions, wherein each logical netlist abstraction corresponds to a portion of the netlist that is below a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein each logical netlist abstraction comprises a center object that is electrically connected to a set of satellite objects, and wherein each satellite object corresponds to a port of the LH node; and wherein each physical block netlist abstraction comprises one or more logical netlist abstractions, wherein each logical netlist abstraction corresponds to a portion of the netlist that is below a logical hierarchy (LH) node in an LH of the netlist of the circuit design, wherein each logical netlist abstraction comprises a center object that is electrically connected to a set of satellite objects, and wherein each satellite object corresponds to a port of the LH node.