# US 10,372,858 B2 · Design-for-testability (DFT) insertion at register-transfer-level (RTL)

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- Number: US 10,372,858 B2
- Document ID: US10372858B2
- Status: Granted
- Kind: B2
- Application number: 15/445,689
- Filed: 2017-02-28
- Published: 2018-08-30
- Granted: 2019-08-06
- Earliest claimed: 2017-02-28
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Eyal Odiz; Janet L. Olson; Mukund Sivaraman
- Web page: https://patentgrep.com/patent/US10372858B2

## CPC

- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.

## Claims

### Claim 1

A non-transitory computer-readable storage medium storing instructions for an integrated circuit (IC) design tool that, when executed by a computer, cause the computer to perform a method for producing a synthesized IC design that includes design-for-testability (DFT) circuitry, the method comprising:
receiving a register-transfer-level (RTL) representation of an IC design that includes functional logic;
adding DFT logic to the RTL representation;
adding a set of anchor points to the RTL representation;
electrically connecting the DFT logic with the set of anchor points; and
performing synthesis on the RTL representation to obtain the synthesized IC design, wherein said performing synthesis on the RTL representation comprises performing a set of operations, the set of operations including:
placing the functional logic and the DFT logic,
electrically disconnecting the DFT logic from the set of anchor points,
removing the set of anchor points,
inserting and placing scan chains, and
electrically connecting the DFT logic with the scan chains; and
wherein adding the DFT logic to the RTL representation, and placing the DFT logic based on the set of anchor points improves a runtime of the IC design tool and/or a quality of results (QoR) produced by the IC design tool.

### Claim 2 (depends on 1)

The non-transitory computer-readable storage medium of claim 1, wherein each anchor point in the set of anchor points is a dummy cell having zero area.

### Claim 3 (depends on 1)

The non-transitory computer-readable storage medium of claim 1, wherein prior to said adding the DFT logic to the RTL representation, the RTL representation does not include any DFT logic and also does not include any scan chains.

### Claim 4 (depends on 1)

The non-transitory computer-readable storage medium of claim 1, wherein prior to said performing synthesis on the RTL representation, the RTL representation does not include physical location information for the functional logic or the DFT logic.

### Claim 5 (depends on 1)

The non-transitory computer-readable storage medium of claim 1, wherein said electrically connecting the DFT logic with the scan chains comprises:
electrically connecting outputs of decompression logic with inputs of the scan chains; and
electrically connecting outputs of the scan chains with inputs of compression logic.

### Claim 6

A method for producing a synthesized integrated circuit (IC) design that includes design-for-testability (DFT) circuitry, the method comprising:
an IC design tool in a computer receiving a register-transfer-level (RTL) representation of an IC design that includes functional logic;
the IC design tool in the computer adding DFT logic to the RTL representation;
adding a set of anchor points to the RTL representation;
electrically connecting the DFT logic with the set of anchor points; and
the IC design tool in the computer performing synthesis on the RTL representation to obtain the synthesized IC design, wherein said performing synthesis on the RTL representation comprises performing a set of operations, the set of operations including:
placing the functional logic and the DFT logic,
electrically disconnecting the DFT logic from the set of anchor points,
removing the set of anchor points,
inserting and placing scan chains, and
electrically connecting the DFT logic with the scan chains; and
wherein adding the DFT logic to the RTL representation, and placing the DFT logic based on the set of anchor points improves a runtime of the IC design tool and/or a quality of results (QoR) produced by the IC design tool.

### Claim 7 (depends on 6)

The method of claim 6, wherein each anchor point in the set of anchor points is a dummy cell having zero area.

### Claim 8 (depends on 6)

The method of claim 6, wherein prior to said adding the DFT logic to the RTL representation, the RTL representation does not include any DFT logic and also does not include any scan chains.

### Claim 9 (depends on 6)

The method of claim 6, wherein prior to said performing synthesis on the RTL representation, the RTL representation does not include physical location information for the functional logic or the DFT logic.

### Claim 10 (depends on 6)

The method of claim 6, wherein said electrically connecting the DFT logic with the scan chains comprises:
electrically connecting outputs of decompression logic with inputs of the scan chains; and
electrically connecting outputs of the scan chains with inputs of compression logic.

### Claim 11

An apparatus, comprising:
a processor; and
a non-transitory computer-readable storage medium storing instructions for an integrated circuit (IC) design tool that, when executed by the processor, cause the apparatus to perform a method for producing a synthesized IC design that includes design-for-testability (DFT) circuitry, the method comprising:
receiving a register-transfer-level (RTL) representation of an IC design that includes functional logic;
adding DFT logic to the RTL representation;
adding a set of anchor points to the RTL representation;
electrically connecting the DFT logic with the set of anchor points; and
performing synthesis on the RTL representation to obtain the synthesized IC design, wherein said performing synthesis on the RTL representation comprises performing a set of operations, the set of operations including:
placing the functional logic and the DFT logic,
electrically disconnecting the DFT logic from the set of anchor points,
removing the set of anchor points,
inserting and placing scan chains, and
electrically connecting the DFT logic with the scan chains; and
wherein adding the DFT logic to the RTL representation, and placing the DFT logic based on the set of anchor points improves a runtime of the IC design tool and/or a quality of results (QoR) produced by the IC design tool.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein prior to said adding the DFT logic to the RTL representation, the RTL representation does not include any DFT logic and also does not include any scan chains.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein prior to said performing synthesis on the RTL representation, the RTL representation does not include physical location information for the functional logic or the DFT logic.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein said electrically connecting the DFT logic with the scan chains comprises:
electrically connecting outputs of decompression logic with inputs of the scan chains; and
electrically connecting outputs of the scan chains with inputs of compression logic.