# US 10,372,852 B2 · Measurement of Aggressor/Victim capacitive coupling impact on timing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,852 B2 - Document ID: US10372852B2 - Status: Granted - Kind: B2 - Application number: 14/748,219 - Filed: 2015-06-23 - Published: 2015-12-24 - Granted: 2019-08-06 - Earliest claimed: 2014-06-24 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Jamil Kawa; Thu Nguyen; Shih-Yao Christine Sun - Web page: https://patentgrep.com/patent/US10372852B2 ## CPC - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 2119/10: Noise analysis or noise optimisation - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A circuit for modeling capacitive coupling comprising a victim line to be tested, a first aggressor line, running alongside the victim line, creating a coupling capacitance between the victim line and the first aggressor line, and a sensor circuit coupled to the victim line, to detect effects of the first aggressor line on the victim line, the sensor circuit measuring timing effects in pseudo-real time. ## Claims ### Claim 1 A circuit including capacitive coupling comprising: a victim line to be tested; a first aggressor line, running alongside the victim line, creating a coupling capacitance between the victim line and the first aggressor line; and a sensor circuit coupled to the victim line, to detect effects of the first aggressor line on the victim line, the sensor circuit measuring timing effects of the capacitive coupling in pseudo-real time and storing the measured time effects for use by an EDA system for designing circuit layout, wherein the sensor circuit is a ring oscillator, the circuit further comprising a feedback loop from an output of the ring oscillator to the victim line. ### Claim 2 (depends on 1) The circuit of claim 1, further comprising: a plurality of coupling capacitances distributed along the victim line and the first aggressor line, to distribute the capacitance along the lines. ### Claim 3 (depends on 2) The circuit of claim 2, further comprising: a plurality of buffers placed along the victim line and the aggressor line, the plurality of coupling capacitances connected between the lines separated by the buffers. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the buffer along the victim line and the corresponding buffer along the aggressor line are matched in size. ### Claim 5 (depends on 3) The circuit of claim 3, wherein measurements are taken along the victim line between the buffers to allow different measurements of capacitive coupling on the victim line. ### Claim 6 (depends on 1) The circuit of claim 1, further comprising: a second aggressor line, running alongside the victim line, allowing detection of the effects of the combination of the first and second aggressor line on the victim line. ### Claim 7 (depends on 1) The circuit of claim 1, wherein measurements taken along the victim line are used to build a characterization table for use in circuit design. ### Claim 8 (depends on 1) The circuit of claim 1, further comprising: input buffers to buffer inputs to the victim line and the aggressor line, the buffered inputs allowing adjustment of the signal of the victim line and the aggressor line from constructive interference to destructive interference. ### Claim 9 (depends on 8) The circuit of claim 8, wherein the adjustment of capacitive offset is performed by the buffered inputs. ### Claim 10 A method for capturing capacitive coupling in an integrated circuit, performed by the integrated circuit, comprising: measuring the output of a victim line of the integrated circuit, the integrated circuit including a plurality of lines carrying signals, the plurality of lines creating capacitive coupling between the victim line and a first aggressor line, the first aggressor line running alongside the victim line in the integrated circuit, the measuring performed through a sensor circuit coupled to the victim line, to detect timing effects of the first aggressor line on the victim line, the sensor circuit measuring the timing effects in pseudo-real time, wherein the sensor circuit is a ring oscillator, the circuit further comprising a feedback loop from an output of the ring oscillator to the victim line; and distributing the capacitive coupling along the victim line and the first aggressor line; and storing the measured output of the victim line so that the measured output can be use by an EDA system for designing circuit layout. ### Claim 11 (depends on 10) The method of claim 10, wherein the measuring may be measured between buffers in the integrated circuit separating the capacitive coupling elements. ### Claim 12 (depends on 10) The method of claim 10, further comprising: when the integrated circuit comprises a second aggressor line running alongside the victim line, detecting the effects of the combination of the first and second aggressor line on the victim line. ### Claim 13 (depends on 10) The method of claim 10, further comprising: building a characterization table based on the output of the sensor circuit, for use in circuit design. ### Claim 14 (depends on 10) The method of claim 10, further comprising: adjusting timing of the signal for the victim line and the aggressor line from constructive interference to destructive interference. ### Claim 15 A system to characterize an impact of capacitive coupling comprising: a circuit including a victim line and a first aggressor line, the first aggressor line running alongside the victim line, creating a plurality of coupling capacitance factors between the victim line and the first aggressor line, and a sensor circuit coupled to the victim line, to detect effects of the first aggressor line on the victim line, the sensor circuit measuring timing effects in pseudo-real time, wherein the sensor circuit is a ring oscillator, the circuit further comprising a feedback loop from an output of the ring oscillator to the victim line; a memory to store the measured timing effects; and an electronic design automation (EDA) tool to utilize the measured timing effects in designing circuit layouts. ### Claim 16 (depends on 15) The system of claim 15, further comprising: a plurality of matched buffers placed along the victim line and the first aggressor line, the plurality of coupling capacitances connected between the lines separated by the plurality of matched buffers. ### Claim 17 (depends on 16) The system of claim 16, wherein the measurements are taken along the victim line between the buffers, to allow different measurements of capacitive coupling on the victim line. ### Claim 18 (depends on 15) The system of claim 15, further comprising: input buffers to adjust the signal switching in the victim line and the aggressor line to test from constructive interference to destructive interference.