# US 10,372,851 B2 · Independently projecting a canonical clock > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,851 B2 - Document ID: US10372851B2 - Status: Granted - Kind: B2 - Application number: 15/592,351 - Filed: 2017-05-11 - Published: 2018-11-15 - Granted: 2019-08-06 - Earliest claimed: 2017-05-11 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Nathan Buck; Sean M. Carey; Peter C. Elmendorf; Eric A. Foreman; Jeffrey G. Hemmett; Lyle Jackson; Kerim Kalafala; Stephen G. Shuma; Michael H. Wood - Web page: https://patentgrep.com/patent/US10372851B2 ## CPC - G06F 30/3315: using static timing analysis [STA] - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/3312: Timing analysis - G06F 30/343: Logical level - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/30: Circuit design - G06F 2111/08: Probabilistic or stochastic CAD - G06F 2119/12: Timing analysis or timing optimisation - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation. ## Claims ### Claim 1 A method comprising: loading a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into a computing device; defining at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation; using said computing device to perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data; projecting a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical; outputting results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design; determining that said performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design is satisfactory; responsive to said determining, instantiating said at least one circuit path of said at least a portion of said integrated circuit design into a design structure; and fabricating a physical integrated circuit including a physical manifestation of said at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure. ### Claim 2 (depends on 1) The method of claim 1, wherein: said slack canonical data is characterized in a canonical slack equation comprising a plurality of terms, each of said terms in turn comprising a mean value plus or minus a predetermined number of standard deviations times a corresponding sensitivity; at least a first one of said plurality of terms corresponds to a cycle time canonical form; at least a second one of said plurality of terms corresponds to a logic canonical form; and said clock period is projected to said different space via said predetermined number of standard deviations for said cycle time canonical form being different than said logic canonical form. ### Claim 3 (depends on 2) The method of claim 2, wherein said at least one canonical clock variable includes a plurality of sources of variation and wherein said cycle time canonical form and said logic canonical form have different ones of said sources of variation. ### Claim 4 (depends on 3) The method of claim 3, wherein said plurality of sources of variation comprise at least one Gaussian source of variation and at least one non-Gaussian source of variation. ### Claim 5 (depends on 2) The method of claim 2, wherein: said canonical slack comprises a canonical clock arrival time term plus a canonical cycle time term less a canonical data arrival time term less a canonical guard time term; said canonical cycle time term comprises said at least first one of said plurality of terms corresponding to said cycle time canonical form; said canonical clock arrival term, said canonical guard time term, and said canonical data arrival time term comprise said at least second one of said plurality of terms corresponding to said logic canonical form. ### Claim 6 (depends on 1) The method of claim 1, further comprising enhancing computational efficiency by projecting said clock period, based on said slack canonical data, such that said cycle time canonical is projected to said different space than said logic canonical, without extra clock timing constraints. ### Claim 7 (depends on 1) The method of claim 1, wherein said cycle time canonical depends on said at least one non-Gaussian source of variation and said logic canonical depends on said at least one Gaussian source of variation. ### Claim 8 (depends on 1) The method of claim 1, further comprising enhancing computational efficiency by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation. ### Claim 9 (depends on 1) The method of claim 1, wherein said at least one canonical clock variable which includes said at least one source of variation comprises a subset of a total number of variables in said statistical static timing analysis (SSTA). ### Claim 10 (depends on 1) The method of claim 1, wherein, during said statistical static timing analysis (SSTA) of said at least one circuit path, said cycle time canonical changes due to downstream slack stealing. ### Claim 11 (depends on 1) The method of claim 1, further comprising providing a system, wherein the system comprises distinct software modules, each of the distinct software modules being embodied on a computer-readable storage medium, and wherein the distinct software modules comprise a projection engine module, a statistical static timing analysis (SSTA) engine module, and a design fixup engine module; wherein: said statistical static timing analysis (SSTA) is carried out by said statistical static timing analysis (SSTA) engine module executing on at least one hardware processor; said projecting of said clock period is carried out by said projection engine module executing on said at least one hardware processor; and said outputting of said results is carried out by said design fixup engine module executing on said at least one hardware processor. ### Claim 12 A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer cause the computer to perform the method of: loading a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into a computing device; defining at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation; using said computing device to perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data; projecting a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical; outputting results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design; determining that said performance compliance of said adjusted at least one circuit path of said at least a portion of said integrated circuit design is satisfactory; responsive to said determining, instantiating said adjusted at least one circuit path of said at least a portion of said integrated circuit design into a design structure; and fabricating a physical integrated circuit including a physical manifestation of said adjusted at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure. ### Claim 13 (depends on 12) The non-transitory computer readable medium of claim 12, wherein: said slack canonical data is characterized in a canonical slack equation comprising a plurality of terms, each of said terms in turn comprising a mean value plus or minus a predetermined number of standard deviations times a corresponding sensitivity; at least a first one of said plurality of terms corresponds to a cycle time canonical form; at least a second one of said plurality of terms corresponds to a logic canonical form; and said clock period is projected to said different space via said predetermined number of standard deviations for said cycle time canonical form being different than said logic canonical form. ### Claim 14 (depends on 13) The non-transitory computer readable medium of claim 13, wherein said at least one canonical clock variable includes a plurality of sources of variation and wherein said cycle time canonical form and said logic canonical form have different ones of said sources of variation. ### Claim 15 (depends on 14) The non-transitory computer readable medium of claim 14, wherein said plurality of sources of variation comprise at least one Gaussian source of variation and at least one non-Gaussian source of variation. ### Claim 16 An apparatus comprising: a memory; and at least one processor, coupled to said memory, and operative to: load a design and timing model for at least one circuit path of at least a portion of an integrated circuit design into said memory; define at least one canonical clock variable associated with said design and timing model, wherein said at least one canonical clock variable includes at least one source of variation; perform a statistical static timing analysis (SSTA) of said at least one circuit path, based on said design and timing model and said at least one canonical clock variable, to obtain slack canonical data; project a clock period, based on said slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical; output results of said statistical static timing analysis (SSTA) and said projected clock period in a form for determining performance compliance of said at least one circuit path of said at least a portion of said integrated circuit design; determining that said performance compliance of said adjusted at least one circuit path of said at least a portion of said integrated circuit design is satisfactory; responsive to said determining, instantiating said adjusted at least one circuit path of said at least a portion of said integrated circuit design into a design structure; and fabricating a physical integrated circuit including a physical manifestation of said adjusted at least one circuit path of said at least a portion of said integrated circuit design, based on said design structure. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein: said slack canonical data is characterized in a canonical slack equation comprising a plurality of terms, each of said terms in turn comprising a mean value plus or minus a predetermined number of standard deviations times a corresponding sensitivity; at least a first one of said plurality of terms corresponds to a cycle time canonical form; at least a second one of said plurality of terms corresponds to a logic canonical form; and said clock period is projected to said different space via said predetermined number of standard deviations for said cycle time canonical form being different than said logic canonical form.