# US 10,372,837 B2 · Integrated circuit buffering solutions considering sink delays

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- Number: US 10,372,837 B2
- Document ID: US10372837B2
- Status: Granted
- Kind: B2
- Application number: 15/896,176
- Filed: 2018-02-14
- Published: 2018-12-27
- Granted: 2019-08-06
- Earliest claimed: 2017-06-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ying Zhou; Stephen T. Quay; Lakshmi N. Reddy; Gustavo E. Tellez; Gi-Joon Nam; Jiang Hu
- Web page: https://patentgrep.com/patent/US10372837B2

## CPC

- G06F 30/3312: Timing analysis
- G06F 30/00: Computer-aided design [CAD]
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

## Claims

### Claim 1

A method for optimizing timing in a very large scale integrated (VLSI) circuit comprising:
traversing a VLSI circuit, the circuit comprising a source, at least one sink, and one or more nodes, each node having a required time and an arrival time, wherein a difference between a node's required time and the node's arrival time is the node's slack, wherein a negative slack value is a delay;
generating, according to the traversing, a set of buffer solutions for the VLSI circuit;
determining a load cap, a buffer cost, a most critical delay, and a sum of delays for each solution in the set of solutions, the most critical delay for each solution found by calculating the delay at each node and identifying the node with the largest delay, the sum of delays for a solution found by taking a measurement, from the sink to the source, of each delay in the solution;
quantifying, for each solution, a relationship between the most critical delay and the sum of delays by calculating a p-norm of the sum of delays;
characterizing each solution according to the solution's load cap, buffer cost, and relationship;
comparing each solution's characterization to the characterization of each other solution in the set of solutions;
identifying, based on the comparing, at least one solution in the set of solutions to have a worse characterization than the other solutions in the set of solutions, wherein a solution has a worse characterization if the solution has:
a load cap with a lower value than at least one other solution of the set of solutions;
a buffer cost with a higher value that at least one other solution of the set of solutions; and
a p-norm of the sum of delays that has a higher value than a p-norm of the sum of delays of at least one other solution of the set of solutions;
pruning the at least one solution from the set of solutions;
iteratively performing the steps of comparing solution's characterizations, identifying at least one solution with a worst characterization, and pruning the at least one solution until a target number of solutions remains; the target number of solutions determined according to a set of design parameters;
submitting at least one remaining solution to an integrated circuit design process;
displaying the at least one submitted solution on a user interface.