# US 10,372,668 B2 · Hardware processors and methods for tightly-coupled heterogeneous computing

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- Number: US 10,372,668 B2
- Document ID: US10372668B2
- Status: Granted
- Kind: B2
- Application number: 15/870,632
- Filed: 2018-01-12
- Published: 2018-08-09
- Granted: 2019-08-06
- Earliest claimed: 2015-06-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chang Yong Kang; Pierre Laurent; Hari K. Tadepalli; Prasad M. Ghatigar; T.J. O'Dwyer; Serge Zhilyaev
- Web page: https://patentgrep.com/patent/US10372668B2

## CPC

- G06F 15/8061: {Details on data memory access}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/3853: {of compound instructions}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks}
- G06F 13/4059: {where the synchronisation uses buffers, e.g. for speed matching between buses}
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 15/8084: {Special arrangements thereof, e.g. mask or switch}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

## Claims

### Claim 1

An apparatus comprising:
a plurality of execution units;
at least one switch to:
connect parallel inputs of the plurality of execution units to an output of a first buffer and parallel outputs of a plurality of memory banks based on a first control value, and
connect parallel inputs of the plurality of memory banks and parallel inputs of a plurality of second buffers to an output of the first buffer, the parallel outputs of the plurality of memory banks, and parallel outputs of the plurality of execution units based on a second control value; and
an offload engine with parallel inputs connected to respective, parallel outputs of the plurality of second buffers.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein an output of the offload engine connects to an input of the first buffer.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the offload engine simultaneously writes to the input of the first buffer and reads from the parallel inputs of the plurality of second buffers.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein data hazard resolution logic circuitry is to not insert a stall.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the plurality of execution units are to execute at a first clock speed and the offload engine is to execute at a second, slower clock speed.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the plurality of execution units each includes a shift register.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first buffer and the plurality of second buffers are first in first out (FIFO) buffers.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the plurality of memory banks are four or more memory banks and each memory bank includes an input port and an output port separate from input ports and output ports of the other memory banks.

### Claim 9

A method comprising:
connecting parallel inputs of a plurality of execution units of a hardware processor to an output of a first buffer and parallel outputs of a plurality of memory banks based on a first control value;
connecting parallel inputs of the plurality of memory banks and parallel inputs of a plurality of second buffers to an output of the first buffer, the parallel outputs of the plurality of memory banks, and parallel outputs of the plurality of execution units based on a second control value; and
providing data to parallel inputs of an offload engine from respective, parallel outputs of the plurality of second buffers.

### Claim 10 (depends on 9)

The method of claim 9, further comprising providing data from an output of the offload engine to an input of the first buffer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising simultaneously reading writing to the input of the first buffer and reading from the parallel inputs of the plurality of second buffers by the offload engine.

### Claim 12 (depends on 11)

The method of claim 11, further comprising not inserting a stall.

### Claim 13 (depends on 9)

The method of claim 9, further comprising the plurality of execution units executing at a first clock speed and the offload engine executing at a second, slower clock speed.

### Claim 14 (depends on 9)

The method of claim 9, wherein the plurality of execution units each includes a shift register.

### Claim 15 (depends on 9)

The method of claim 9, wherein the plurality of memory banks are four or more memory banks and each memory bank includes an input port and an output port separate from input ports and output ports of the other memory banks.

### Claim 16 (depends on 9)

The method of claim 9, wherein the first buffer and the plurality of second buffers are first in first out (FIFO) buffers.

### Claim 17

A hardware processor comprising:
a hardware decoder to decode an instruction into a decoded instruction;
a hardware execution unit to execute the decoded instruction to:
connect parallel inputs of a plurality of execution units of a hardware processor to an output of a first buffer and parallel outputs of a plurality of memory banks based on a first field of the instruction;
connect parallel inputs of the plurality of memory banks and parallel inputs of a plurality of second buffers to an output of the first buffer, the parallel outputs of the plurality of memory banks, and parallel outputs of the plurality of execution units based on a second field of the instruction; and
provide data to parallel inputs of an offload engine from respective, parallel outputs of the plurality of second buffers.

### Claim 18 (depends on 17)

The hardware processor of claim 17, wherein an output of the offload engine connects to an input of the first buffer.

### Claim 19 (depends on 18)

The hardware processor of claim 18, wherein the hardware execution unit is to execute the instruction to cause a simultaneous write to the input of the first buffer and reads from the parallel inputs of the plurality of second buffers.

### Claim 20 (depends on 19)

The hardware processor of claim 19, wherein the hardware execution unit is to execute the instruction without inserting a stall.

### Claim 21 (depends on 17)

The hardware processor of claim 17, wherein the plurality of execution units are to execute at a first clock speed and the offload engine is to execute at a second, slower clock speed.

### Claim 22 (depends on 17)

The hardware processor of claim 17, wherein the plurality of execution units each includes a shift register.

### Claim 23 (depends on 17)

The hardware processor of claim 17, wherein the first buffer and the plurality of second buffers are first in first out (FIFO) buffers.

### Claim 24 (depends on 17)

The hardware processor of claim 17, wherein the plurality of memory banks are four or more memory banks and each memory bank includes an input port and an output port separate from input ports and output ports of the other memory banks.