# US 10,372,663 B2 · Short address mode for communicating waveform > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,663 B2 - Document ID: US10372663B2 - Status: Granted - Kind: B2 - Application number: 15/658,748 - Filed: 2017-07-25 - Published: 2019-01-31 - Granted: 2019-08-06 - Earliest claimed: 2017-07-25 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Kyu Hak Kim; Guangming Bu - Web page: https://patentgrep.com/patent/US10372663B2 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation - G06F 2213/0016: Inter-integrated circuit (I2C) - G06F 2213/0052: Assignment of addresses or identifiers to the modules of a bus system - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems, methods, and apparatus for data communication are provided. A device operating as a bus master may be detect one or more slaves on a serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address. The bus master may then calculate a number of slave address bits needed to address the one or more slaves in a binary form based on a quantity of the one or more slaves and generate shortened slave addresses for the one or more slaves, respectively. A length of each shortened slave address is the number of slave address bits. The bus master may then assign a generated shortened slave address to each of the one or more slaves and send the waveform to a slave via the serial bus using an assigned shortened slave address. ## Claims ### Claim 1 A method performed at a device operating as a bus master, comprising: detecting one or more slaves on a serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address; calculating a number of slave address bits needed to address the one or more slaves in a binary form based on a quantity of the one or more slaves; generating shortened slave addresses for the one or more slaves, respectively, wherein a length of each shortened slave address is the number of slave address bits; assigning a generated shortened slave address to each of the one or more slaves; sending a first indication to a slave to activate the shortened address mode; sending the waveform to the slave via the serial bus using an assigned shortened slave address; and sending a second indication to the slave to deactivate the shortened address mode. ### Claim 2 (depends on 1) The method of claim 1, wherein the number of slave address bits is less than 7 bits. ### Claim 3 (depends on 1) The method of claim 1, wherein: the calculated number of slave address bits is 1 bit if the quantity of the one or more slaves is 1 slave; the calculated number of slave address bits is 2 bits if the quantity of the one or more slaves is 2 to 4 slaves; the calculated number of slave address bits is 3 bits if the quantity of the one or more slaves is 5 to 8 slaves; and the calculated number of slave address bits is 4 bits if the quantity of the one or more slaves is 9 to 16 slaves. ### Claim 4 (depends on 1) The method of claim 1, further including: detecting a quantity of registers within the slave; calculating a number of register address bits needed to address registers in a binary form based on the quantity of registers; generating shortened register addresses for the registers, respectively, wherein a length of each shortened register address is the number of register address bits; and assigning a generated shortened register address to each of the registers, wherein the waveform is sent to the slave using an assigned shortened register address. ### Claim 5 (depends on 4) The method of claim 4, wherein the number of register address bits is less than 8 bits. ### Claim 6 (depends on 4) The method of claim 4, wherein: the calculated number of register address bits is 1 bit if the quantity of registers is 1 register; the calculated number of register address bits is 2 bits if the quantity of registers is 2 to 4 registers; the calculated number of register address bits is 3 bits if the quantity of registers is 5 to 8 registers; the calculated number of register address bits is 4 bits if the quantity of registers is 9 to 16 registers; and the calculated number of register address bits is 5 bits if the quantity of registers is 17 to 32 registers. ### Claim 7 (depends on 4) The method of claim 4, wherein: the detecting includes detecting whether the slave supports a reduced field mode or a combined address mode, the assigned shortened slave address and the assigned shortened register address occupy different fields in the waveform if the slave supports the reduced field mode, and the assigned shortened slave address and the assigned shortened register address occupy a same field in the waveform if the slave supports the combined address mode. ### Claim 8 A bus master apparatus, comprising: an interface circuit configured to couple the bus master apparatus to a serial bus; and a processing circuit configured to: detect one or more slaves on the serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address, calculate a number of slave address bits needed to address the one or more slaves in a binary form based on a quantity of the one or more slaves, generate shortened slave addresses for the one or more slaves, respectively, wherein a length of each shortened slave address is the number of slave address bits, assign a generated shortened slave address to each of the one or more slaves, send a first indication to a slave to activate the shortened address mode, send the waveform to the slave via the serial bus using an assigned shortened slave address, and send a second indication to the slave to deactivate the shortened address mode. ### Claim 9 (depends on 8) The bus master apparatus of claim 8, wherein the number of slave address bits is less than 7 bits. ### Claim 10 (depends on 8) The bus master apparatus of claim 8, wherein the processing circuit is further configured to: detect a quantity of registers within the slave; calculate a number of register address bits needed to address registers in a binary form based on the quantity of registers; generate shortened register addresses for the registers, respectively, wherein a length of each shortened register address is the number of register address bits; and assign a generated shortened register address to each of the registers, wherein the waveform is sent to the slave using an assigned shortened register address. ### Claim 11 (depends on 10) The bus master apparatus of claim 10, wherein the number of register address bits is less than 8 bits. ### Claim 12 (depends on 10) The bus master apparatus of claim 10, wherein: the processing circuit is further configured to detect whether the slave supports a reduced field mode or a combined address mode, the assigned shortened slave address and the assigned shortened register address occupy different fields in the waveform if the slave supports the reduced field mode, and the assigned shortened slave address and the assigned shortened register address occupy a same field in the waveform if the slave supports the combined address mode. ### Claim 13 A method performed at a slave coupled to a serial bus, comprising: indicating to a bus master that the slave supports a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address; receiving from the bus master an assignment of the shortened slave address, wherein a length of the shortened slave address is equivalent to a number of slave address bits needed to address in a binary form a quantity of slaves on the serial bus supporting the shortened address mode; receiving a first indication from the bus master to activate the shortened address mode; receiving the waveform from the bus master based on the assigned shortened slave address; and receiving a second indication from the bus master to deactivate the shortened address mode. ### Claim 14 (depends on 13) The method of claim 13, wherein the number of slave address bits is less than 7 bits. ### Claim 15 (depends on 13) The method of claim 13, wherein: the number of slave address bits is 1 bit if the quantity of slaves is 1 slave; the number of slave address bits is 2 bits if the quantity of slaves is 2 to 4 slaves; the number of slave address bits is 3 bits if the quantity of slaves is 5 to 8 slaves; and the number of slave address bits is 4 bits if the quantity of slaves is 9 to 16 slaves. ### Claim 16 (depends on 13) The method of claim 13, further including: indicating to the bus master a quantity of registers within the slave; and receiving from the bus master an assignment of shortened register addresses for the quantity of registers, respectively, wherein a length of each shortened register address is equivalent to a number of register address bits needed to address in a binary form the quantity of registers, wherein the waveform is received from the bus master based on an assigned shortened register address. ### Claim 17 (depends on 16) The method of claim 16, wherein the number of register address bits is less than 8 bits. ### Claim 18 (depends on 16) The method of claim 16, wherein: the number of register address bits is 1 bit if the quantity of registers is 1 register; the number of register address bits is 2 bits if the quantity of registers is 2 to 4 registers; the number of register address bits is 3 bits if the quantity of registers is 5 to 8 registers; the number of register address bits is 4 bits if the quantity of registers is 9 to 16 registers; and the number of register address bits is 5 bits if the quantity of registers is 17 to 32 registers. ### Claim 19 (depends on 16) The method of claim 16, wherein: the indicating includes indicating whether the slave supports a reduced field mode or a combined address mode, the assigned shortened slave address and the assigned shortened register address occupy different fields in the waveform if the slave supports the reduced field mode, and the assigned shortened slave address and the assigned shortened register address occupy a same field in the waveform if the slave supports the combined address mode. ### Claim 20 A slave device, comprising: an interface circuit configured to couple the slave device to a serial bus; and a processing circuit configured to: indicate to a bus master that the slave device supports a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address; receive from the bus master an assignment of the shortened slave address, wherein a length of the shortened slave address is equivalent to a number of slave address bits needed to address in a binary form a quantity of slaves on the serial bus supporting the shortened address mode; receive a first indication from the bus master to activate the shortened address mode; receive the waveform from the bus master based on the assigned shortened slave address; and receive a second indication from the bus master to deactivate the shortened address mode. ### Claim 21 (depends on 20) The slave device of claim 20, wherein the number of slave address bits is less than 7 bits. ### Claim 22 (depends on 20) The slave device of claim 20, wherein the processing circuit is further configured to: indicate to the bus master a quantity of registers within the slave device; and receive from the bus master an assignment of shortened register addresses for the quantity of registers, respectively, wherein a length of each shortened register address is equivalent to a number of register address bits needed to address in a binary form the quantity of registers, wherein the waveform is received from the bus master based on an assigned shortened register address. ### Claim 23 (depends on 22) The slave device of claim 22, wherein the number of register address bits is less than 8 bits. ### Claim 24 (depends on 22) The slave device of claim 22, wherein: the processing circuit is further configured to indicate whether the slave device supports a reduced field mode or a combined address mode, the assigned shortened slave address and the assigned shortened register address occupy different fields in the waveform if the slave device supports the reduced field mode, and the assigned shortened slave address and the assigned shortened register address occupy a same field in the waveform if the slave device supports the combined address mode.